UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'mips-next-3.10' of git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next

This commit is contained in:
Ralf Baechle 2013-05-08 01:27:46 +02:00
parent 3d39019a16 1cd1c04927
commit 9b3539e0e5
1267 changed files with 15334 additions and 7665 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
CREDITS
View File

@ -1510,6 +1510,14 @@ D: Natsemi ethernet
D: Cobalt Networks (x86) support
D: This-and-That
N: Mark M. Hoffman
E: mhoffman@lightlink.com
D: asb100, lm93 and smsc47b397 hardware monitoring drivers
D: hwmon subsystem core
D: hwmon subsystem maintainer
D: i2c-sis96x and i2c-stub SMBus drivers
S: USA
N: Dirk Hohndel
E: hohndel@suse.de
D: The XFree86[tm] Project

2
Documentation/DocBook/device-drivers.tmpl
View File

@ -227,7 +227,7 @@ X!Isound/sound_firmware.c
<chapter id="uart16x50">
<title>16x50 UART Driver</title>
!Edrivers/tty/serial/serial_core.c
!Edrivers/tty/serial/8250/8250.c
!Edrivers/tty/serial/8250/8250_core.c
</chapter>
<chapter id="fbdev">

6
Documentation/devicetree/bindings/mfd/ab8500.txt
View File

@ -13,9 +13,6 @@ Required parent device properties:
4 = active high level-sensitive
8 = active low level-sensitive
Optional parent device properties:
- reg : contains the PRCMU mailbox address for the AB8500 i2c port
The AB8500 consists of a large and varied group of sub-devices:
Device IRQ Names Supply Names Description
@ -86,9 +83,8 @@ Non-standard child device properties:
- stericsson,amic2-bias-vamic1 : Analoge Mic wishes to use a non-standard Vamic
- stericsson,earpeice-cmv : Earpeice voltage (only: 950 | 1100 | 1270 | 1580)
ab8500@5 {
ab8500 {
compatible = "stericsson,ab8500";
reg = <5>; /* mailbox 5 is i2c */
interrupts = <0 40 0x4>;
interrupt-controller;
#interrupt-cells = <2>;

17
Documentation/devicetree/bindings/mips/ralink.txt Normal file
View File

@ -0,0 +1,17 @@
Ralink MIPS SoC device tree bindings
1. SoCs
Each device tree must specify a compatible value for the Ralink SoC
it uses in the compatible property of the root node. The compatible
value must be one of the following values:
ralink,rt2880-soc
ralink,rt3050-soc
ralink,rt3052-soc
ralink,rt3350-soc
ralink,rt3352-soc
ralink,rt3883-soc
ralink,rt5350-soc
ralink,mt7620a-soc
ralink,mt7620n-soc

3
Documentation/devicetree/bindings/tty/serial/of-serial.txt
View File

@ -11,6 +11,9 @@ Required properties:
- "nvidia,tegra20-uart"
- "nxp,lpc3220-uart"
- "ibm,qpace-nwp-serial"
- "altr,16550-FIFO32"
- "altr,16550-FIFO64"
- "altr,16550-FIFO128"
- "serial" if the port type is unknown.
- reg : offset and length of the register set for the device.
- interrupts : should contain uart interrupt.

1
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -41,6 +41,7 @@ onnn ON Semiconductor Corp.
picochip Picochip Ltd
powervr PowerVR (deprecated, use img)
qcom Qualcomm, Inc.
ralink Mediatek/Ralink Technology Corp.
ramtron Ramtron International
realtek Realtek Semiconductor Corp.
renesas Renesas Electronics Corporation

2
Documentation/hwmon/lm75
View File

@ -23,7 +23,7 @@ Supported chips:
Datasheet: Publicly available at the Maxim website
http://www.maxim-ic.com/
* Microchip (TelCom) TCN75
Prefix: 'lm75'
Prefix: 'tcn75'
Addresses scanned: none
Datasheet: Publicly available at the Microchip website
http://www.microchip.com/

2
Documentation/i2c/busses/i2c-diolan-u2c
View File

@ -5,7 +5,7 @@ Supported adapters:
Documentation:
http://www.diolan.com/i2c/u2c12.html
Author: Guenter Roeck <guenter.roeck@ericsson.com>
Author: Guenter Roeck <linux@roeck-us.net>
Description
-----------

65
Documentation/input/alps.txt
View File

@ -3,10 +3,26 @@ ALPS Touchpad Protocol
Introduction
------------
Currently the ALPS touchpad driver supports five protocol versions in use by
ALPS touchpads, called versions 1, 2, 3, 4 and 5.
Currently the ALPS touchpad driver supports four protocol versions in use by
ALPS touchpads, called versions 1, 2, 3, and 4. Information about the various
protocol versions is contained in the following sections.
Since roughly mid-2010 several new ALPS touchpads have been released and
integrated into a variety of laptops and netbooks. These new touchpads
have enough behavior differences that the alps_model_data definition
table, describing the properties of the different versions, is no longer
adequate. The design choices were to re-define the alps_model_data
table, with the risk of regression testing existing devices, or isolate
the new devices outside of the alps_model_data table. The latter design
choice was made. The new touchpad signatures are named: "Rushmore",
"Pinnacle", and "Dolphin", which you will see in the alps.c code.
For the purposes of this document, this group of ALPS touchpads will
generically be called "new ALPS touchpads".
We experimented with probing the ACPI interface _HID (Hardware ID)/_CID
(Compatibility ID) definition as a way to uniquely identify the
different ALPS variants but there did not appear to be a 1:1 mapping.
In fact, it appeared to be an m:n mapping between the _HID and actual
hardware type.
Detection
---------
@ -20,9 +36,13 @@ If the E6 report is successful, the touchpad model is identified using the "E7
report" sequence: E8-E7-E7-E7-E9. The response is the model signature and is
matched against known models in the alps_model_data_array.
With protocol versions 3 and 4, the E7 report model signature is always
73-02-64. To differentiate between these versions, the response from the
"Enter Command Mode" sequence must be inspected as described below.
For older touchpads supporting protocol versions 3 and 4, the E7 report
model signature is always 73-02-64. To differentiate between these
versions, the response from the "Enter Command Mode" sequence must be
inspected as described below.
The new ALPS touchpads have an E7 signature of 73-03-50 or 73-03-0A but
seem to be better differentiated by the EC Command Mode response.
Command Mode
------------
@ -47,6 +67,14 @@ address of the register being read, and the third contains the value of the
register. Registers are written by writing the value one nibble at a time
using the same encoding used for addresses.
For the new ALPS touchpads, the EC command is used to enter command
mode. The response in the new ALPS touchpads is significantly different,
and more important in determining the behavior. This code has been
separated from the original alps_model_data table and put in the
alps_identify function. For example, there seem to be two hardware init
sequences for the "Dolphin" touchpads as determined by the second byte
of the EC response.
Packet Format
-------------
@ -187,3 +215,28 @@ There are several things worth noting here.
well.
So far no v4 devices with tracksticks have been encountered.
ALPS Absolute Mode - Protocol Version 5
---------------------------------------
This is basically Protocol Version 3 but with different logic for packet
decode. It uses the same alps_process_touchpad_packet_v3 call with a
specialized decode_fields function pointer to correctly interpret the
packets. This appears to only be used by the Dolphin devices.
For single-touch, the 6-byte packet format is:
byte 0: 1 1 0 0 1 0 0 0
byte 1: 0 x6 x5 x4 x3 x2 x1 x0
byte 2: 0 y6 y5 y4 y3 y2 y1 y0
byte 3: 0 M R L 1 m r l
byte 4: y10 y9 y8 y7 x10 x9 x8 x7
byte 5: 0 z6 z5 z4 z3 z2 z1 z0
For mt, the format is:
byte 0: 1 1 1 n3 1 n2 n1 x24
byte 1: 1 y7 y6 y5 y4 y3 y2 y1
byte 2: ? x2 x1 y12 y11 y10 y9 y8
byte 3: 0 x23 x22 x21 x20 x19 x18 x17
byte 4: 0 x9 x8 x7 x6 x5 x4 x3
byte 5: 0 x16 x15 x14 x13 x12 x11 x10

7
Documentation/networking/ipvs-sysctl.txt
View File

@ -15,6 +15,13 @@ amemthresh - INTEGER
enabled and the variable is automatically set to 2, otherwise
the strategy is disabled and the variable is set to 1.
backup_only - BOOLEAN
0 - disabled (default)
not 0 - enabled
If set, disable the director function while the server is
in backup mode to avoid packet loops for DR/TUN methods.
conntrack - BOOLEAN
0 - disabled (default)
not 0 - enabled

77
Documentation/networking/tuntap.txt
View File

@ -105,6 +105,83 @@ Copyright (C) 1999-2000 Maxim Krasnyansky <max_mk@yahoo.com>
Proto [2 bytes]
Raw protocol(IP, IPv6, etc) frame.
3.3 Multiqueue tuntap interface:
From version 3.8, Linux supports multiqueue tuntap which can uses multiple
file descriptors (queues) to parallelize packets sending or receiving. The
device allocation is the same as before, and if user wants to create multiple
queues, TUNSETIFF with the same device name must be called many times with
IFF_MULTI_QUEUE flag.
char *dev should be the name of the device, queues is the number of queues to
be created, fds is used to store and return the file descriptors (queues)
created to the caller. Each file descriptor were served as the interface of a
queue which could be accessed by userspace.
#include <linux/if.h>
#include <linux/if_tun.h>
int tun_alloc_mq(char *dev, int queues, int *fds)
{
struct ifreq ifr;
int fd, err, i;
if (!dev)
return -1;
memset(&ifr, 0, sizeof(ifr));
/* Flags: IFF_TUN - TUN device (no Ethernet headers)
* IFF_TAP - TAP device
*
* IFF_NO_PI - Do not provide packet information
* IFF_MULTI_QUEUE - Create a queue of multiqueue device
*/
ifr.ifr_flags = IFF_TAP | IFF_NO_PI | IFF_MULTI_QUEUE;
strcpy(ifr.ifr_name, dev);
for (i = 0; i < queues; i++) {
if ((fd = open("/dev/net/tun", O_RDWR)) < 0)
goto err;
err = ioctl(fd, TUNSETIFF, (void *)&ifr);
if (err) {
close(fd);
goto err;
}
fds[i] = fd;
}
return 0;
err:
for (--i; i >= 0; i--)
close(fds[i]);
return err;
}
A new ioctl(TUNSETQUEUE) were introduced to enable or disable a queue. When
calling it with IFF_DETACH_QUEUE flag, the queue were disabled. And when
calling it with IFF_ATTACH_QUEUE flag, the queue were enabled. The queue were
enabled by default after it was created through TUNSETIFF.
fd is the file descriptor (queue) that we want to enable or disable, when
enable is true we enable it, otherwise we disable it
#include <linux/if.h>
#include <linux/if_tun.h>
int tun_set_queue(int fd, int enable)
{
struct ifreq ifr;
memset(&ifr, 0, sizeof(ifr));
if (enable)
ifr.ifr_flags = IFF_ATTACH_QUEUE;
else
ifr.ifr_flags = IFF_DETACH_QUEUE;
return ioctl(fd, TUNSETQUEUE, (void *)&ifr);
}
Universal TUN/TAP device driver Frequently Asked Question.
1. What platforms are supported by TUN/TAP driver ?

2
Documentation/scsi/LICENSE.qla2xxx
View File

@ -1,4 +1,4 @@
Copyright (c) 2003-2012 QLogic Corporation
Copyright (c) 2003-2013 QLogic Corporation
QLogic Linux FC-FCoE Driver
This program includes a device driver for Linux 3.x.

7
Documentation/sound/alsa/ALSA-Configuration.txt
View File

@ -890,9 +890,8 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
enable_msi - Enable Message Signaled Interrupt (MSI) (default = off)
power_save - Automatic power-saving timeout (in second, 0 =
disable)
power_save_controller - Support runtime D3 of HD-audio controller
(-1 = on for supported chip (default), false = off,
true = force to on even for unsupported hardware)
power_save_controller - Reset HD-audio controller in power-saving mode
(default = on)
align_buffer_size - Force rounding of buffer/period sizes to multiples
of 128 bytes. This is more efficient in terms of memory
access but isn't required by the HDA spec and prevents
@ -912,7 +911,7 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
models depending on the codec chip. The list of available models
is found in HD-Audio-Models.txt
The model name "genric" is treated as a special case. When this
The model name "generic" is treated as a special case. When this
model is given, the driver uses the generic codec parser without
"codec-patch". It's sometimes good for testing and debugging.

2
Documentation/sound/alsa/seq_oss.html
View File

@ -285,7 +285,7 @@ sample data.
<H4>
7.2.4 Close Callback</H4>
The <TT>close</TT> callback is called when this device is closed by the
applicaion. If any private data was allocated in open callback, it must
application. If any private data was allocated in open callback, it must
be released in the close callback. The deletion of ALSA port should be
done here, too. This callback must not be NULL.
<H4>

2
Documentation/trace/ftrace.txt
View File

@ -1873,7 +1873,7 @@ feature:
status\input | 0 | 1 | else |
--------------+------------+------------+------------+
not allocated |(do nothing)| alloc+swap | EINVAL |
not allocated |(do nothing)| alloc+swap |(do nothing)|
--------------+------------+------------+------------+
allocated | free | swap | clear |
--------------+------------+------------+------------+

102
MAINTAINERS
View File

@ -1338,12 +1338,6 @@ S: Maintained
F: drivers/platform/x86/asus*.c
F: drivers/platform/x86/eeepc*.c
ASUS ASB100 HARDWARE MONITOR DRIVER
M: "Mark M. Hoffman" <mhoffman@lightlink.com>
L: lm-sensors@lm-sensors.org
S: Maintained
F: drivers/hwmon/asb100.c
ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API
M: Dan Williams <djbw@fb.com>
W: http://sourceforge.net/projects/xscaleiop
@ -1467,6 +1461,12 @@ F: drivers/dma/at_hdmac.c
F: drivers/dma/at_hdmac_regs.h
F: include/linux/platform_data/dma-atmel.h
ATMEL I2C DRIVER
M: Ludovic Desroches <ludovic.desroches@atmel.com>
L: linux-i2c@vger.kernel.org
S: Supported
F: drivers/i2c/busses/i2c-at91.c
ATMEL ISI DRIVER
M: Josh Wu <josh.wu@atmel.com>
L: linux-media@vger.kernel.org
@ -2629,7 +2629,7 @@ F: include/uapi/drm/
INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets)
M: Daniel Vetter <daniel.vetter@ffwll.ch>
L: intel-gfx@lists.freedesktop.org (subscribers-only)
L: intel-gfx@lists.freedesktop.org
L: dri-devel@lists.freedesktop.org
T: git git://people.freedesktop.org/~danvet/drm-intel
S: Supported
@ -3242,6 +3242,12 @@ F: Documentation/firmware_class/
F: drivers/base/firmware*.c
F: include/linux/firmware.h
FLASHSYSTEM DRIVER (IBM FlashSystem 70/80 PCI SSD Flash Card)
M: Joshua Morris <josh.h.morris@us.ibm.com>
M: Philip Kelleher <pjk1939@linux.vnet.ibm.com>
S: Maintained
F: drivers/block/rsxx/
FLOPPY DRIVER
M: Jiri Kosina <jkosina@suse.cz>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jikos/floppy.git
@ -3851,7 +3857,7 @@ F: drivers/i2c/busses/i2c-ismt.c
F: Documentation/i2c/busses/i2c-ismt
I2C/SMBUS STUB DRIVER
M: "Mark M. Hoffman" <mhoffman@lightlink.com>
M: Jean Delvare <khali@linux-fr.org>
L: linux-i2c@vger.kernel.org
S: Maintained
F: drivers/i2c/i2c-stub.c
@ -4005,6 +4011,22 @@ M: Stanislaw Gruszka <stf_xl@wp.pl>
S: Maintained
F: drivers/usb/atm/ueagle-atm.c
INA209 HARDWARE MONITOR DRIVER
M: Guenter Roeck <linux@roeck-us.net>
L: lm-sensors@lm-sensors.org
S: Maintained
F: Documentation/hwmon/ina209
F: Documentation/devicetree/bindings/i2c/ina209.txt
F: drivers/hwmon/ina209.c
INA2XX HARDWARE MONITOR DRIVER
M: Guenter Roeck <linux@roeck-us.net>
L: lm-sensors@lm-sensors.org
S: Maintained
F: Documentation/hwmon/ina2xx
F: drivers/hwmon/ina2xx.c
F: include/linux/platform_data/ina2xx.h
INDUSTRY PACK SUBSYSTEM (IPACK)
M: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
M: Jens Taprogge <jens.taprogge@taprogge.org>
@ -4919,6 +4941,12 @@ W: logfs.org
S: Maintained
F: fs/logfs/
LPC32XX MACHINE SUPPORT
M: Roland Stigge <stigge@antcom.de>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-lpc32xx/
LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI)
M: Nagalakshmi Nandigama <Nagalakshmi.Nandigama@lsi.com>
M: Sreekanth Reddy <Sreekanth.Reddy@lsi.com>
@ -5043,9 +5071,8 @@ S: Maintained
F: drivers/net/ethernet/marvell/sk*
MARVELL LIBERTAS WIRELESS DRIVER
M: Dan Williams <dcbw@redhat.com>
L: libertas-dev@lists.infradead.org
S: Maintained
S: Orphan
F: drivers/net/wireless/libertas/
MARVELL MV643XX ETHERNET DRIVER
@ -5098,6 +5125,15 @@ S: Maintained
F: Documentation/hwmon/max6650
F: drivers/hwmon/max6650.c
MAX6697 HARDWARE MONITOR DRIVER
M: Guenter Roeck <linux@roeck-us.net>
L: lm-sensors@lm-sensors.org
S: Maintained
F: Documentation/hwmon/max6697
F: Documentation/devicetree/bindings/i2c/max6697.txt
F: drivers/hwmon/max6697.c
F: include/linux/platform_data/max6697.h
MAXIRADIO FM RADIO RECEIVER DRIVER
M: Hans Verkuil <hverkuil@xs4all.nl>
L: linux-media@vger.kernel.org
@ -5538,6 +5574,7 @@ F: include/uapi/linux/if_*
F: include/uapi/linux/netdevice.h
NETXEN (1/10) GbE SUPPORT
M: Manish Chopra <manish.chopra@qlogic.com>
M: Sony Chacko <sony.chacko@qlogic.com>
M: Rajesh Borundia <rajesh.borundia@qlogic.com>
L: netdev@vger.kernel.org
@ -5622,6 +5659,14 @@ S: Maintained
F: drivers/video/riva/
F: drivers/video/nvidia/
NVM EXPRESS DRIVER
M: Matthew Wilcox <willy@linux.intel.com>
L: linux-nvme@lists.infradead.org
T: git git://git.infradead.org/users/willy/linux-nvme.git
S: Supported
F: drivers/block/nvme.c
F: include/linux/nvme.h
OMAP SUPPORT
M: Tony Lindgren <tony@atomide.com>
L: linux-omap@vger.kernel.org
@ -5650,7 +5695,7 @@ S: Maintained
F: arch/arm/*omap*/*clock*
OMAP POWER MANAGEMENT SUPPORT
M: Kevin Hilman <khilman@ti.com>
M: Kevin Hilman <khilman@deeprootsystems.com>
L: linux-omap@vger.kernel.org
S: Maintained
F: arch/arm/*omap*/*pm*
@ -5744,7 +5789,7 @@ F: arch/arm/*omap*/usb*
OMAP GPIO DRIVER
M: Santosh Shilimkar <santosh.shilimkar@ti.com>
M: Kevin Hilman <khilman@ti.com>
M: Kevin Hilman <khilman@deeprootsystems.com>
L: linux-omap@vger.kernel.org
S: Maintained
F: drivers/gpio/gpio-omap.c
@ -6176,7 +6221,7 @@ F: include/linux/power_supply.h
F: drivers/power/
PNP SUPPORT
M: Adam Belay <abelay@mit.edu>
M: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
M: Bjorn Helgaas <bhelgaas@google.com>
S: Maintained
F: drivers/pnp/
@ -6412,6 +6457,8 @@ F: Documentation/networking/LICENSE.qla3xxx
F: drivers/net/ethernet/qlogic/qla3xxx.*
QLOGIC QLCNIC (1/10)Gb ETHERNET DRIVER
M: Rajesh Borundia <rajesh.borundia@qlogic.com>
M: Shahed Shaikh <shahed.shaikh@qlogic.com>
M: Jitendra Kalsaria <jitendra.kalsaria@qlogic.com>
M: Sony Chacko <sony.chacko@qlogic.com>
M: linux-driver@qlogic.com
@ -6516,12 +6563,6 @@ S: Maintained
F: Documentation/blockdev/ramdisk.txt
F: drivers/block/brd.c
RAMSAM DRIVER (IBM RamSan 70/80 PCI SSD Flash Card)
M: Joshua Morris <josh.h.morris@us.ibm.com>
M: Philip Kelleher <pjk1939@linux.vnet.ibm.com>
S: Maintained
F: drivers/block/rsxx/
RANDOM NUMBER DRIVER
M: Theodore Ts'o" <tytso@mit.edu>
S: Maintained
@ -6590,7 +6631,7 @@ S: Supported
F: fs/reiserfs/
REGISTER MAP ABSTRACTION
M: Mark Brown <broonie@opensource.wolfsonmicro.com>
M: Mark Brown <broonie@kernel.org>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git
S: Supported
F: drivers/base/regmap/
@ -6916,7 +6957,6 @@ F: drivers/scsi/st*
SCTP PROTOCOL
M: Vlad Yasevich <vyasevich@gmail.com>
M: Sridhar Samudrala <sri@us.ibm.com>
M: Neil Horman <nhorman@tuxdriver.com>
L: linux-sctp@vger.kernel.org
W: http://lksctp.sourceforge.net
@ -7138,7 +7178,7 @@ F: arch/arm/mach-s3c2410/bast-irq.c
TI DAVINCI MACHINE SUPPORT
M: Sekhar Nori <nsekhar@ti.com>
M: Kevin Hilman <khilman@ti.com>
M: Kevin Hilman <khilman@deeprootsystems.com>
L: davinci-linux-open-source@linux.davincidsp.com (moderated for non-subscribers)
T: git git://gitorious.org/linux-davinci/linux-davinci.git
Q: http://patchwork.kernel.org/project/linux-davinci/list/
@ -7171,13 +7211,6 @@ L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ethernet/sis/sis900.*
SIS 96X I2C/SMBUS DRIVER
M: "Mark M. Hoffman" <mhoffman@lightlink.com>
L: linux-i2c@vger.kernel.org
S: Maintained
F: Documentation/i2c/busses/i2c-sis96x
F: drivers/i2c/busses/i2c-sis96x.c
SIS FRAMEBUFFER DRIVER
M: Thomas Winischhofer <thomas@winischhofer.net>
W: http://www.winischhofer.net/linuxsisvga.shtml
@ -7255,7 +7288,7 @@ F: Documentation/hwmon/sch5627
F: drivers/hwmon/sch5627.c
SMSC47B397 HARDWARE MONITOR DRIVER
M: "Mark M. Hoffman" <mhoffman@lightlink.com>
M: Jean Delvare <khali@linux-fr.org>
L: lm-sensors@lm-sensors.org
S: Maintained
F: Documentation/hwmon/smsc47b397
@ -7346,7 +7379,7 @@ F: sound/
SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEMENT (ASoC)
M: Liam Girdwood <lgirdwood@gmail.com>
M: Mark Brown <broonie@opensource.wolfsonmicro.com>
M: Mark Brown <broonie@kernel.org>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
W: http://alsa-project.org/main/index.php/ASoC
@ -7435,7 +7468,7 @@ F: drivers/clk/spear/
SPI SUBSYSTEM
M: Grant Likely <grant.likely@secretlab.ca>
M: Mark Brown <broonie@opensource.wolfsonmicro.com>
M: Mark Brown <broonie@kernel.org>
L: spi-devel-general@lists.sourceforge.net
Q: http://patchwork.kernel.org/project/spi-devel-general/list/
T: git git://git.secretlab.ca/git/linux-2.6.git
@ -7678,9 +7711,10 @@ F: include/linux/swiotlb.h
SYNOPSYS ARC ARCHITECTURE
M: Vineet Gupta <vgupta@synopsys.com>
L: linux-snps-arc@vger.kernel.org
S: Supported
F: arch/arc/
F: Documentation/devicetree/bindings/arc/
F: drivers/tty/serial/arc-uart.c
SYSV FILESYSTEM
M: Christoph Hellwig <hch@infradead.org>
@ -8679,7 +8713,7 @@ F: drivers/scsi/vmw_pvscsi.h
VOLTAGE AND CURRENT REGULATOR FRAMEWORK
M: Liam Girdwood <lrg@ti.com>
M: Mark Brown <broonie@opensource.wolfsonmicro.com>
M: Mark Brown <broonie@kernel.org>
W: http://opensource.wolfsonmicro.com/node/15
W: http://www.slimlogic.co.uk/?p=48
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lrg/regulator.git

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 9
SUBLEVEL = 0
EXTRAVERSION = -rc2
EXTRAVERSION = -rc7
NAME = Unicycling Gorilla
# *DOCUMENTATION*

7
arch/Kconfig
View File

@ -319,13 +319,6 @@ config ARCH_WANT_OLD_COMPAT_IPC
select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
bool
config HAVE_VIRT_TO_BUS
bool
help
An architecture should select this if it implements the
deprecated interface virt_to_bus(). All new architectures
should probably not select this.
config HAVE_ARCH_SECCOMP_FILTER
bool
help

2
arch/alpha/Kconfig
View File

@ -9,7 +9,7 @@ config ALPHA
select HAVE_PERF_EVENTS
select HAVE_DMA_ATTRS
select HAVE_GENERIC_HARDIRQS
select HAVE_VIRT_TO_BUS
select VIRT_TO_BUS
select GENERIC_IRQ_PROBE
select AUTO_IRQ_AFFINITY if SMP
select GENERIC_IRQ_SHOW

2
arch/alpha/Makefile
View File

@ -12,7 +12,7 @@ NM := $(NM) -B
LDFLAGS_vmlinux := -static -N #-relax
CHECKFLAGS += -D__alpha__ -m64
cflags-y := -pipe -mno-fp-regs -ffixed-8 -msmall-data
cflags-y := -pipe -mno-fp-regs -ffixed-8
cflags-y += $(call cc-option, -fno-jump-tables)
cpuflags-$(CONFIG_ALPHA_EV4) := -mcpu=ev4

2
arch/alpha/include/asm/floppy.h
View File

@ -26,7 +26,7 @@
#define fd_disable_irq() disable_irq(FLOPPY_IRQ)
#define fd_cacheflush(addr,size) /* nothing */
#define fd_request_irq() request_irq(FLOPPY_IRQ, floppy_interrupt,\
IRQF_DISABLED, "floppy", NULL)
0, "floppy", NULL)
#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL)
#ifdef CONFIG_PCI

7
arch/alpha/kernel/irq.c
View File

@ -117,13 +117,6 @@ handle_irq(int irq)
return;
}
/*
* From here we must proceed with IPL_MAX. Note that we do not
* explicitly enable interrupts afterwards - some MILO PALcode
* (namely LX164 one) seems to have severe problems with RTI
* at IPL 0.
*/
local_irq_disable();
irq_enter();
generic_handle_irq_desc(irq, desc);
irq_exit();

10
arch/alpha/kernel/irq_alpha.c
View File

@ -45,6 +45,14 @@ do_entInt(unsigned long type, unsigned long vector,
unsigned long la_ptr, struct pt_regs *regs)
{
struct pt_regs *old_regs;
/*
* Disable interrupts during IRQ handling.
* Note that there is no matching local_irq_enable() due to
* severe problems with RTI at IPL0 and some MILO PALcode
* (namely LX164).
*/
local_irq_disable();
switch (type) {
case 0:
#ifdef CONFIG_SMP
@ -62,7 +70,6 @@ do_entInt(unsigned long type, unsigned long vector,
{
long cpu;
local_irq_disable();
smp_percpu_timer_interrupt(regs);
cpu = smp_processor_id();
if (cpu != boot_cpuid) {
@ -222,7 +229,6 @@ process_mcheck_info(unsigned long vector, unsigned long la_ptr,
struct irqaction timer_irqaction = {
.handler = timer_interrupt,
.flags = IRQF_DISABLED,
.name = "timer",
};

5
arch/alpha/kernel/sys_nautilus.c
View File

@ -188,6 +188,10 @@ nautilus_machine_check(unsigned long vector, unsigned long la_ptr)
extern void free_reserved_mem(void *, void *);
extern void pcibios_claim_one_bus(struct pci_bus *);
static struct resource irongate_io = {
.name = "Irongate PCI IO",
.flags = IORESOURCE_IO,
};
static struct resource irongate_mem = {
.name = "Irongate PCI MEM",
.flags = IORESOURCE_MEM,
@ -209,6 +213,7 @@ nautilus_init_pci(void)
irongate = pci_get_bus_and_slot(0, 0);
bus->self = irongate;
bus->resource[0] = &irongate_io;
bus->resource[1] = &irongate_mem;
pci_bus_size_bridges(bus);

14
arch/alpha/kernel/sys_titan.c
View File

@ -280,15 +280,15 @@ titan_late_init(void)
* all reported to the kernel as machine checks, so the handler
* is a nop so it can be called to count the individual events.
*/
titan_request_irq(63+16, titan_intr_nop, IRQF_DISABLED,
titan_request_irq(63+16, titan_intr_nop, 0,
"CChip Error", NULL);
titan_request_irq(62+16, titan_intr_nop, IRQF_DISABLED,
titan_request_irq(62+16, titan_intr_nop, 0,
"PChip 0 H_Error", NULL);
titan_request_irq(61+16, titan_intr_nop, IRQF_DISABLED,
titan_request_irq(61+16, titan_intr_nop, 0,
"PChip 1 H_Error", NULL);
titan_request_irq(60+16, titan_intr_nop, IRQF_DISABLED,
titan_request_irq(60+16, titan_intr_nop, 0,
"PChip 0 C_Error", NULL);
titan_request_irq(59+16, titan_intr_nop, IRQF_DISABLED,
titan_request_irq(59+16, titan_intr_nop, 0,
"PChip 1 C_Error", NULL);
/*
@ -348,9 +348,9 @@ privateer_init_pci(void)
* Hook a couple of extra err interrupts that the
* common titan code won't.
*/
titan_request_irq(53+16, titan_intr_nop, IRQF_DISABLED,
titan_request_irq(53+16, titan_intr_nop, 0,
"NMI", NULL);
titan_request_irq(50+16, titan_intr_nop, IRQF_DISABLED,
titan_request_irq(50+16, titan_intr_nop, 0,
"Temperature Warning", NULL);
/*

2
arch/arc/include/asm/dma-mapping.h
View File

@ -126,7 +126,7 @@ dma_map_sg(struct device *dev, struct scatterlist *sg,
int i;
for_each_sg(sg, s, nents, i)
sg->dma_address = dma_map_page(dev, sg_page(s), s->offset,
s->dma_address = dma_map_page(dev, sg_page(s), s->offset,
s->length, dir);
return nents;

3
arch/arc/include/asm/elf.h
View File

@ -72,7 +72,4 @@ extern int elf_check_arch(const struct elf32_hdr *);
*/
#define ELF_PLATFORM (NULL)
#define SET_PERSONALITY(ex) \
set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
#endif

2
arch/arc/include/asm/entry.h
View File

@ -415,7 +415,7 @@
*-------------------------------------------------------------*/
.macro SAVE_ALL_EXCEPTION marker
st \marker, [sp, 8]
st \marker, [sp, 8] /* orig_r8 */
st r0, [sp, 4] /* orig_r0, needed only for sys calls */
/* Restore r9 used to code the early prologue */

12
arch/arc/include/asm/irqflags.h
View File

@ -39,7 +39,7 @@ static inline long arch_local_irq_save(void)
" flag.nz %0 \n"
: "=r"(temp), "=r"(flags)
: "n"((STATUS_E1_MASK | STATUS_E2_MASK))
: "cc");
: "memory", "cc");
return flags;
}
@ -53,7 +53,8 @@ static inline void arch_local_irq_restore(unsigned long flags)
__asm__ __volatile__(
" flag %0 \n"
:
: "r"(flags));
: "r"(flags)
: "memory");
}
/*
@ -73,7 +74,8 @@ static inline void arch_local_irq_disable(void)
" and %0, %0, %1 \n"
" flag %0 \n"
: "=&r"(temp)
: "n"(~(STATUS_E1_MASK | STATUS_E2_MASK)));
: "n"(~(STATUS_E1_MASK | STATUS_E2_MASK))
: "memory");
}
/*
@ -85,7 +87,9 @@ static inline long arch_local_save_flags(void)
__asm__ __volatile__(
" lr %0, [status32] \n"
: "=&r"(temp));
: "=&r"(temp)
:
: "memory");
return temp;
}

6
arch/arc/include/asm/kgdb.h
View File

@ -13,7 +13,7 @@
#ifdef CONFIG_KGDB
#include <asm/user.h>
#include <asm/ptrace.h>
/* to ensure compatibility with Linux 2.6.35, we don't implement the get/set
* register API yet */
@ -53,9 +53,7 @@ enum arc700_linux_regnums {
};
#else
static inline void kgdb_trap(struct pt_regs *regs, int param)
{
}
#define kgdb_trap(regs, param)
#endif
#endif /* __ARC_KGDB_H__ */

2
arch/arc/include/asm/ptrace.h
View File

@ -123,7 +123,7 @@ static inline long regs_return_value(struct pt_regs *regs)
#define orig_r8_IS_SCALL 0x0001
#define orig_r8_IS_SCALL_RESTARTED 0x0002
#define orig_r8_IS_BRKPT 0x0004
#define orig_r8_IS_EXCPN 0x0004
#define orig_r8_IS_EXCPN 0x0008
#define orig_r8_IS_IRQ1 0x0010
#define orig_r8_IS_IRQ2 0x0020

2
arch/arc/include/asm/syscalls.h
View File

@ -16,8 +16,6 @@
#include <linux/types.h>
int sys_clone_wrapper(int, int, int, int, int);
int sys_fork_wrapper(void);
int sys_vfork_wrapper(void);
int sys_cacheflush(uint32_t, uint32_t uint32_t);
int sys_arc_settls(void *);
int sys_arc_gettls(void);

4
arch/arc/include/uapi/asm/ptrace.h
View File

@ -28,14 +28,14 @@
*/
struct user_regs_struct {
struct scratch {
struct {
long pad;
long bta, lp_start, lp_end, lp_count;
long status32, ret, blink, fp, gp;
long r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0;
long sp;
} scratch;
struct callee {
struct {
long pad;
long r25, r24, r23, r22, r21, r20;
long r19, r18, r17, r16, r15, r14, r13;

27
arch/arc/kernel/entry.S
View File

@ -452,7 +452,7 @@ tracesys:
; using ERET won't work since next-PC has already committed
lr r12, [efa]
GET_CURR_TASK_FIELD_PTR TASK_THREAD, r11
st r12, [r11, THREAD_FAULT_ADDR]
st r12, [r11, THREAD_FAULT_ADDR] ; thread.fault_address
; PRE Sys Call Ptrace hook
mov r0, sp ; pt_regs needed
@ -792,31 +792,6 @@ ARC_EXIT ret_from_fork
;################### Special Sys Call Wrappers ##########################
; TBD: call do_fork directly from here
ARC_ENTRY sys_fork_wrapper
SAVE_CALLEE_SAVED_USER
bl @sys_fork
DISCARD_CALLEE_SAVED_USER
GET_CURR_THR_INFO_FLAGS r10
btst r10, TIF_SYSCALL_TRACE
bnz tracesys_exit
b ret_from_system_call
ARC_EXIT sys_fork_wrapper
ARC_ENTRY sys_vfork_wrapper
SAVE_CALLEE_SAVED_USER
bl @sys_vfork
DISCARD_CALLEE_SAVED_USER
GET_CURR_THR_INFO_FLAGS r10
btst r10, TIF_SYSCALL_TRACE
bnz tracesys_exit
b ret_from_system_call
ARC_EXIT sys_vfork_wrapper
ARC_ENTRY sys_clone_wrapper
SAVE_CALLEE_SAVED_USER
bl @sys_clone

1
arch/arc/kernel/kgdb.c
View File

@ -9,6 +9,7 @@
*/
#include <linux/kgdb.h>
#include <linux/sched.h>
#include <asm/disasm.h>
#include <asm/cacheflush.h>

4
arch/arc/kernel/setup.c
View File

@ -232,10 +232,8 @@ char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
n += scnprintf(buf + n, len - n, "\n");
#ifdef _ASM_GENERIC_UNISTD_H
n += scnprintf(buf + n, len - n,
"OS ABI [v2]\t: asm-generic/{unistd,stat,fcntl}\n");
#endif
"OS ABI [v3]\t: no-legacy-syscalls\n");
return buf;
}

2
arch/arc/kernel/sys.c
View File

@ -6,8 +6,6 @@
#include <asm/syscalls.h>
#define sys_clone sys_clone_wrapper
#define sys_fork sys_fork_wrapper
#define sys_vfork sys_vfork_wrapper
#undef __SYSCALL
#define __SYSCALL(nr, call) [nr] = (call),

36
arch/arm/Kconfig
View File

@ -49,7 +49,6 @@ config ARM
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_SYSCALL_TRACEPOINTS
select HAVE_UID16
select HAVE_VIRT_TO_BUS
select KTIME_SCALAR
select PERF_USE_VMALLOC
select RTC_LIB
@ -556,7 +555,6 @@ config ARCH_IXP4XX
config ARCH_DOVE
bool "Marvell Dove"
select ARCH_REQUIRE_GPIOLIB
select COMMON_CLK_DOVE
select CPU_V7
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_PCI
@ -744,6 +742,7 @@ config ARCH_RPC
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
select NO_IOPORT
select VIRT_TO_BUS
help
On the Acorn Risc-PC, Linux can support the internal IDE disk and
CD-ROM interface, serial and parallel port, and the floppy drive.
@ -879,6 +878,7 @@ config ARCH_SHARK
select ISA_DMA
select NEED_MACH_MEMORY_H
select PCI
select VIRT_TO_BUS
select ZONE_DMA
help
Support for the StrongARM based Digital DNARD machine, also known
@ -1006,12 +1006,12 @@ config ARCH_MULTI_V4_V5
bool
config ARCH_MULTI_V6
bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
bool "ARMv6 based platforms (ARM11)"
select ARCH_MULTI_V6_V7
select CPU_V6
config ARCH_MULTI_V7
bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
default y
select ARCH_MULTI_V6_V7
select ARCH_VEXPRESS
@ -1183,9 +1183,9 @@ config ARM_NR_BANKS
default 8
config IWMMXT
bool "Enable iWMMXt support"
bool "Enable iWMMXt support" if !CPU_PJ4
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
default y if PXA27x || PXA3xx || ARCH_MMP
default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
help
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
@ -1439,6 +1439,16 @@ config ARM_ERRATA_775420
to deadlock. This workaround puts DSB before executing ISB if
an abort may occur on cache maintenance.
config ARM_ERRATA_798181
bool "ARM errata: TLBI/DSB failure on Cortex-A15"
depends on CPU_V7 && SMP
help
On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
adequately shooting down all use of the old entries. This
option enables the Linux kernel workaround for this erratum
which sends an IPI to the CPUs that are running the same ASID
as the one being invalidated.
endmenu
source "arch/arm/common/Kconfig"
@ -1462,10 +1472,6 @@ config ISA_DMA
bool
select ISA_DMA_API
config ARCH_NO_VIRT_TO_BUS
def_bool y
depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
# Select ISA DMA interface
config ISA_DMA_API
bool
@ -1657,13 +1663,16 @@ config LOCAL_TIMERS
accounting to be spread across the timer interval, preventing a
"thundering herd" at every timer tick.
# The GPIO number here must be sorted by descending number. In case of
# a multiplatform kernel, we just want the highest value required by the
# selected platforms.
config ARCH_NR_GPIO
int
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 355 if ARCH_U8500
default 264 if MACH_H4700
default 512 if SOC_OMAP5
default 355 if ARCH_U8500
default 288 if ARCH_VT8500 || ARCH_SUNXI
default 264 if MACH_H4700
default 0
help
Maximum number of GPIOs in the system.
@ -1887,8 +1896,9 @@ config XEN_DOM0
config XEN
bool "Xen guest support on ARM (EXPERIMENTAL)"
depends on ARM && OF
depends on ARM && AEABI && OF
depends on CPU_V7 && !CPU_V6
depends on !GENERIC_ATOMIC64
help
Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.

3
arch/arm/Kconfig.debug
View File

@ -492,9 +492,10 @@ config DEBUG_IMX_UART_PORT
DEBUG_IMX31_UART || \
DEBUG_IMX35_UART || \
DEBUG_IMX51_UART || \
DEBUG_IMX50_IMX53_UART || \
DEBUG_IMX53_UART || \
DEBUG_IMX6Q_UART
default 1
depends on ARCH_MXC
help
Choose UART port on which kernel low-level debug messages
should be output.

2
arch/arm/boot/Makefile
View File

@ -115,4 +115,4 @@ i:
$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
$(obj)/Image System.map "$(INSTALL_PATH)"
subdir- := bootp compressed
subdir- := bootp compressed dts

2
arch/arm/boot/dts/armada-370-mirabox.dts
View File

@ -54,7 +54,7 @@
};
mvsdio@d00d4000 {
pinctrl-0 = <&sdio_pins2>;
pinctrl-0 = <&sdio_pins3>;
pinctrl-names = "default";
status = "okay";
/*

8
arch/arm/boot/dts/armada-370-rd.dts
View File

@ -64,5 +64,13 @@
status = "okay";
/* No CD or WP GPIOs */
};
usb@d0050000 {
status = "okay";
};
usb@d0051000 {
status = "okay";
};
};
};

5
arch/arm/boot/dts/armada-370-xp.dtsi
View File

@ -31,7 +31,6 @@
mpic: interrupt-controller@d0020000 {
compatible = "marvell,mpic";
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
};
@ -54,7 +53,7 @@
reg = <0xd0012000 0x100>;
reg-shift = <2>;
interrupts = <41>;
reg-io-width = <4>;
reg-io-width = <1>;
status = "disabled";
};
serial@d0012100 {
@ -62,7 +61,7 @@
reg = <0xd0012100 0x100>;
reg-shift = <2>;
interrupts = <42>;
reg-io-width = <4>;
reg-io-width = <1>;
status = "disabled";
};

6
arch/arm/boot/dts/armada-370.dtsi
View File

@ -59,6 +59,12 @@
"mpp50", "mpp51", "mpp52";
marvell,function = "sd0";
};
sdio_pins3: sdio-pins3 {
marvell,pins = "mpp48", "mpp49", "mpp50",
"mpp51", "mpp52", "mpp53";
marvell,function = "sd0";
};
};
gpio0: gpio@d0018100 {

4
arch/arm/boot/dts/armada-xp.dtsi
View File

@ -46,7 +46,7 @@
reg = <0xd0012200 0x100>;
reg-shift = <2>;
interrupts = <43>;
reg-io-width = <4>;
reg-io-width = <1>;
status = "disabled";
};
serial@d0012300 {
@ -54,7 +54,7 @@
reg = <0xd0012300 0x100>;
reg-shift = <2>;
interrupts = <44>;
reg-io-width = <4>;
reg-io-width = <1>;
status = "disabled";
};

28
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -238,8 +238,32 @@
nand {
pinctrl_nand: nand-0 {
atmel,pins =
<3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
<3 0 0x1 0x0 /* PD0 periph A Read Enable */
3 1 0x1 0x0 /* PD1 periph A Write Enable */
3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */
3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */
3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */
3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */
3 6 0x1 0x0 /* PD6 periph A Data bit 0 */
3 7 0x1 0x0 /* PD7 periph A Data bit 1 */
3 8 0x1 0x0 /* PD8 periph A Data bit 2 */
3 9 0x1 0x0 /* PD9 periph A Data bit 3 */
3 10 0x1 0x0 /* PD10 periph A Data bit 4 */
3 11 0x1 0x0 /* PD11 periph A Data bit 5 */
3 12 0x1 0x0 /* PD12 periph A Data bit 6 */
3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */
};
pinctrl_nand_16bits: nand_16bits-0 {
atmel,pins =
<3 14 0x1 0x0 /* PD14 periph A Data bit 8 */
3 15 0x1 0x0 /* PD15 periph A Data bit 9 */
3 16 0x1 0x0 /* PD16 periph A Data bit 10 */
3 17 0x1 0x0 /* PD17 periph A Data bit 11 */
3 18 0x1 0x0 /* PD18 periph A Data bit 12 */
3 19 0x1 0x0 /* PD19 periph A Data bit 13 */
3 20 0x1 0x0 /* PD20 periph A Data bit 14 */
3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */
};
};

2
arch/arm/boot/dts/bcm2835.dtsi
View File

@ -105,7 +105,7 @@
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <150000000>;
clock-frequency = <250000000>;
};
};
};

7
arch/arm/boot/dts/dbx5x0.dtsi
View File

@ -191,8 +191,8 @@
prcmu: prcmu@80157000 {
compatible = "stericsson,db8500-prcmu";
reg = <0x80157000 0x1000>;
reg-names = "prcmu";
reg = <0x80157000 0x1000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
interrupts = <0 47 0x4>;
#address-cells = <1>;
#size-cells = <1>;
@ -319,9 +319,8 @@
};
};
ab8500@5 {
ab8500 {
compatible = "stericsson,ab8500";
reg = <5>; /* mailbox 5 is i2c */
interrupt-parent = <&intc>;
interrupts = <0 40 0x4>;
interrupt-controller;

5
arch/arm/boot/dts/dove.dtsi
View File

@ -197,6 +197,11 @@
status = "disabled";
};
rtc@d8500 {
compatible = "marvell,orion-rtc";
reg = <0xd8500 0x20>;
};
crypto: crypto@30000 {
compatible = "marvell,orion-crypto";
reg = <0x30000 0x10000>,

9
arch/arm/boot/dts/exynos4.dtsi
View File

@ -275,18 +275,27 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
interrupts = <0 35 0>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
interrupts = <0 36 0>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
mdma1: mdma@12850000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
interrupts = <0 34 0>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
};
};

6
arch/arm/boot/dts/exynos5440.dtsi
View File

@ -142,12 +142,18 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x120000 0x1000>;
interrupts = <0 34 0>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121000 0x1000>;
interrupts = <0 35 0>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
};

2
arch/arm/boot/dts/href.dtsi
View File

@ -221,7 +221,7 @@
};
};
ab8500@5 {
ab8500 {
ab8500-regulators {
ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
regulator-name = "V-DISPLAY";

2
arch/arm/boot/dts/hrefv60plus.dts
View File

@ -158,7 +158,7 @@
};
};
ab8500@5 {
ab8500 {
ab8500-regulators {
ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
regulator-name = "V-DISPLAY";

1
arch/arm/boot/dts/imx28-m28evk.dts
View File

@ -152,7 +152,6 @@
i2c0: i2c@80058000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
clock-frequency = <400000>;
status = "okay";
sgtl5000: codec@0a {

1
arch/arm/boot/dts/imx28-sps1.dts
View File

@ -70,7 +70,6 @@
i2c0: i2c@80058000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
clock-frequency = <400000>;
status = "okay";
rtc: rtc@51 {

3
arch/arm/boot/dts/imx53-mba53.dts
View File

@ -42,10 +42,9 @@
fsl,pins = <689 0x10000 /* DISP1_DRDY */
482 0x10000 /* DISP1_HSYNC */
489 0x10000 /* DISP1_VSYNC */
684 0x10000 /* DISP1_DAT_0 */
515 0x10000 /* DISP1_DAT_22 */
523 0x10000 /* DISP1_DAT_23 */
543 0x10000 /* DISP1_DAT_21 */
545 0x10000 /* DISP1_DAT_21 */
553 0x10000 /* DISP1_DAT_20 */
558 0x10000 /* DISP1_DAT_19 */
564 0x10000 /* DISP1_DAT_18 */

1
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -91,6 +91,7 @@
compatible = "arm,cortex-a9-twd-timer";
reg = <0x00a00600 0x20>;
interrupts = <1 13 0xf01>;
clocks = <&clks 15>;
};
L2: l2-cache@00a02000 {

2
arch/arm/boot/dts/kirkwood-dns320.dts
View File

@ -42,12 +42,10 @@
ocp@f1000000 {
serial@12000 {
clock-frequency = <166666667>;
status = "okay";
};
serial@12100 {
clock-frequency = <166666667>;
status = "okay";
};
};

1
arch/arm/boot/dts/kirkwood-dns325.dts
View File

@ -50,7 +50,6 @@
};
};
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
};

1
arch/arm/boot/dts/kirkwood-dockstar.dts
View File

@ -37,7 +37,6 @@
};
};
serial@12000 {
clock-frequency = <200000000>;
status = "ok";
};

1
arch/arm/boot/dts/kirkwood-dreamplug.dts
View File

@ -38,7 +38,6 @@
};
};
serial@12000 {
clock-frequency = <200000000>;
status = "ok";
};

2
arch/arm/boot/dts/kirkwood-goflexnet.dts
View File

@ -73,11 +73,11 @@
};
};
serial@12000 {
clock-frequency = <200000000>;
status = "ok";
};
nand@3000000 {
chip-delay = <40>;
status = "okay";
partition@0 {

1
arch/arm/boot/dts/kirkwood-ib62x0.dts
View File

@ -51,7 +51,6 @@
};
};
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};

1
arch/arm/boot/dts/kirkwood-iconnect.dts
View File

@ -78,7 +78,6 @@
};
};
serial@12000 {
clock-frequency = <200000000>;
status = "ok";
};

15
arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
View File

@ -96,11 +96,11 @@
marvell,function = "gpio";
};
pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 {
marvell,pins = "mpp44";
marvell,pins = "mpp46";
marvell,function = "gpio";
};
pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 {
marvell,pins = "mpp45";
marvell,pins = "mpp47";
marvell,function = "gpio";
};
@ -115,7 +115,6 @@
};
serial@12000 {
clock-frequency = <200000000>;
status = "ok";
};
@ -158,14 +157,14 @@
gpios = <&gpio0 16 0>;
linux,default-trigger = "default-on";
};
health_led1 {
rebuild_led {
label = "status:white:rebuild_led";
gpios = <&gpio1 4 0>;
};
health_led {
label = "status:red:health_led";
gpios = <&gpio1 5 0>;
};
health_led2 {
label = "status:white:health_led";
gpios = <&gpio1 4 0>;
};
backup_led {
label = "status:blue:backup_led";
gpios = <&gpio0 15 0>;

1
arch/arm/boot/dts/kirkwood-km_kirkwood.dts
View File

@ -34,7 +34,6 @@
};
serial@12000 {
clock-frequency = <200000000>;
status = "ok";
};

1
arch/arm/boot/dts/kirkwood-lschlv2.dts
View File

@ -13,7 +13,6 @@
ocp@f1000000 {
serial@12000 {
clock-frequency = <166666667>;
status = "okay";
};
};

1
arch/arm/boot/dts/kirkwood-lsxhl.dts
View File

@ -13,7 +13,6 @@
ocp@f1000000 {
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
};

1
arch/arm/boot/dts/kirkwood-mplcec4.dts
View File

@ -90,7 +90,6 @@
};
serial@12000 {
clock-frequency = <200000000>;
status = "ok";
};

1
arch/arm/boot/dts/kirkwood-ns2-common.dtsi
View File

@ -23,7 +23,6 @@
};
serial@12000 {
clock-frequency = <166666667>;
status = "okay";
};

1
arch/arm/boot/dts/kirkwood-nsa310.dts
View File

@ -117,7 +117,6 @@
};
serial@12000 {
clock-frequency = <200000000>;
status = "ok";
};

2
arch/arm/boot/dts/kirkwood-openblocks_a6.dts
View File

@ -18,12 +18,10 @@
ocp@f1000000 {
serial@12000 {
clock-frequency = <200000000>;
status = "ok";
};
serial@12100 {
clock-frequency = <200000000>;
status = "ok";
};

1
arch/arm/boot/dts/kirkwood-topkick.dts
View File

@ -108,7 +108,6 @@
};
serial@12000 {
clock-frequency = <200000000>;
status = "ok";
};

5
arch/arm/boot/dts/kirkwood.dtsi
View File

@ -38,6 +38,7 @@
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <35>, <36>, <37>, <38>;
clocks = <&gate_clk 7>;
};
gpio1: gpio@10140 {
@ -49,6 +50,7 @@
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <39>, <40>, <41>;
clocks = <&gate_clk 7>;
};
serial@12000 {
@ -57,7 +59,6 @@
reg-shift = <2>;
interrupts = <33>;
clocks = <&gate_clk 7>;
/* set clock-frequency in board dts */
status = "disabled";
};
@ -67,7 +68,6 @@
reg-shift = <2>;
interrupts = <34>;
clocks = <&gate_clk 7>;
/* set clock-frequency in board dts */
status = "disabled";
};
@ -75,6 +75,7 @@
compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <53>;
clocks = <&gate_clk 7>;
};
spi@10600 {

2
arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
View File

@ -11,7 +11,7 @@
/ {
model = "LaCie Ethernet Disk mini V2";
compatible = "lacie,ethernet-disk-mini-v2", "marvell-orion5x-88f5182", "marvell,orion5x";
compatible = "lacie,ethernet-disk-mini-v2", "marvell,orion5x-88f5182", "marvell,orion5x";
memory {
reg = <0x00000000 0x4000000>; /* 64 MB */

9
arch/arm/boot/dts/orion5x.dtsi
View File

@ -13,6 +13,9 @@
compatible = "marvell,orion5x";
interrupt-parent = <&intc>;
aliases {
gpio0 = &gpio0;
};
intc: interrupt-controller {
compatible = "marvell,orion-intc", "marvell,intc";
interrupt-controller;
@ -32,7 +35,9 @@
#gpio-cells = <2>;
gpio-controller;
reg = <0x10100 0x40>;
ngpio = <32>;
ngpios = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <6>, <7>, <8>, <9>;
};
@ -91,7 +96,7 @@
reg = <0x90000 0x10000>,
<0xf2200000 0x800>;
reg-names = "regs", "sram";
interrupts = <22>;
interrupts = <28>;
status = "okay";
};
};

2
arch/arm/boot/dts/snowball.dts
View File

@ -298,7 +298,7 @@
};
};
ab8500@5 {
ab8500 {
ab8500-regulators {
ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
regulator-name = "V-DISPLAY";

3
arch/arm/boot/dts/socfpga.dtsi
View File

@ -75,6 +75,9 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0xffe01000 0x1000>;
interrupts = <0 180 4>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
};

3
arch/arm/boot/dts/tegra20.dtsi
View File

@ -118,6 +118,7 @@
compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>;
interrupts = <1 13 0x304>;
clocks = <&tegra_car 132>;
};
intc: interrupt-controller {
@ -384,7 +385,7 @@
spi@7000d800 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d480 0x200>;
reg = <0x7000d800 0x200>;
interrupts = <0 83 0x04>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;

3
arch/arm/boot/dts/tegra30.dtsi
View File

@ -119,6 +119,7 @@
compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>;
interrupts = <1 13 0xf04>;
clocks = <&tegra_car 214>;
};
intc: interrupt-controller {
@ -371,7 +372,7 @@
spi@7000d800 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d480 0x200>;
reg = <0x7000d800 0x200>;
interrupts = <0 83 0x04>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;

1
arch/arm/configs/mxs_defconfig
View File

@ -116,6 +116,7 @@ CONFIG_SND_SOC=y
CONFIG_SND_MXS_SOC=y
CONFIG_SND_SOC_MXS_SGTL5000=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_STORAGE=y

2
arch/arm/configs/omap2plus_defconfig
View File

@ -126,6 +126,8 @@ CONFIG_INPUT_MISC=y
CONFIG_INPUT_TWL4030_PWRBUTTON=y
CONFIG_VT_HW_CONSOLE_BINDING=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=32
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y

2
arch/arm/include/asm/delay.h
View File

@ -24,7 +24,7 @@ extern struct arm_delay_ops {
void (*delay)(unsigned long);
void (*const_udelay)(unsigned long);
void (*udelay)(unsigned long);
bool const_clock;
unsigned long ticks_per_jiffy;
} arm_delay_ops;
#define __delay(n) arm_delay_ops.delay(n)

7
arch/arm/include/asm/highmem.h
View File

@ -41,6 +41,13 @@ extern void kunmap_high(struct page *page);
#endif
#endif
/*
* Needed to be able to broadcast the TLB invalidation for kmap.
*/
#ifdef CONFIG_ARM_ERRATA_798181
#undef ARCH_NEEDS_KMAP_HIGH_GET
#endif
#ifdef ARCH_NEEDS_KMAP_HIGH_GET
extern void *kmap_high_get(struct page *page);
#else

2
arch/arm/include/asm/mmu_context.h
View File

@ -27,6 +27,8 @@ void __check_vmalloc_seq(struct mm_struct *mm);
void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; })
DECLARE_PER_CPU(atomic64_t, active_asids);
#else /* !CONFIG_CPU_HAS_ASID */
#ifdef CONFIG_MMU

15
arch/arm/include/asm/tlbflush.h
View File

@ -450,6 +450,21 @@ static inline void local_flush_bp_all(void)
isb();
}
#ifdef CONFIG_ARM_ERRATA_798181
static inline void dummy_flush_tlb_a15_erratum(void)
{
/*
* Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0.
*/
asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
dsb();
}
#else
static inline void dummy_flush_tlb_a15_erratum(void)
{
}
#endif
/*
* flush_pmd_entry
*

25
arch/arm/include/asm/xen/events.h
View File

@ -2,6 +2,7 @@
#define _ASM_ARM_XEN_EVENTS_H
#include <asm/ptrace.h>
#include <asm/atomic.h>
enum ipi_vector {
XEN_PLACEHOLDER_VECTOR,
@ -15,26 +16,8 @@ static inline int xen_irqs_disabled(struct pt_regs *regs)
return raw_irqs_disabled_flags(regs->ARM_cpsr);
}
/*
* We cannot use xchg because it does not support 8-byte
* values. However it is safe to use {ldr,dtd}exd directly because all
* platforms which Xen can run on support those instructions.
*/
static inline xen_ulong_t xchg_xen_ulong(xen_ulong_t *ptr, xen_ulong_t val)
{
xen_ulong_t oldval;
unsigned int tmp;
wmb();
asm volatile("@ xchg_xen_ulong\n"
"1: ldrexd %0, %H0, [%3]\n"
" strexd %1, %2, %H2, [%3]\n"
" teq %1, #0\n"
" bne 1b"
: "=&r" (oldval), "=&r" (tmp)
: "r" (val), "r" (ptr)
: "memory", "cc");
return oldval;
}
#define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((ptr), \
atomic64_t, \
counter), (val))
#endif /* _ASM_ARM_XEN_EVENTS_H */

12
arch/arm/kernel/entry-common.S
View File

@ -276,7 +276,13 @@ ENDPROC(ftrace_graph_caller_old)
*/
.macro mcount_enter
/*
* This pad compensates for the push {lr} at the call site. Note that we are
* unable to unwind through a function which does not otherwise save its lr.
*/
UNWIND(.pad #4)
stmdb sp!, {r0-r3, lr}
UNWIND(.save {r0-r3, lr})
.endm
.macro mcount_get_lr reg
@ -289,6 +295,7 @@ ENDPROC(ftrace_graph_caller_old)
.endm
ENTRY(__gnu_mcount_nc)
UNWIND(.fnstart)
#ifdef CONFIG_DYNAMIC_FTRACE
mov ip, lr
ldmia sp!, {lr}
@ -296,17 +303,22 @@ ENTRY(__gnu_mcount_nc)
#else
__mcount
#endif
UNWIND(.fnend)
ENDPROC(__gnu_mcount_nc)
#ifdef CONFIG_DYNAMIC_FTRACE
ENTRY(ftrace_caller)
UNWIND(.fnstart)
__ftrace_caller
UNWIND(.fnend)
ENDPROC(ftrace_caller)
#endif
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
ENTRY(ftrace_graph_caller)
UNWIND(.fnstart)
__ftrace_graph_caller
UNWIND(.fnend)
ENDPROC(ftrace_graph_caller)
#endif

2
arch/arm/kernel/head.S
View File

@ -267,7 +267,7 @@ __create_page_tables:
addne r6, r6, #1 << SECTION_SHIFT
strne r6, [r3]
#if defined(CONFIG_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
sub r4, r4, #4 @ Fixup page table pointer
@ for 64-bit descriptors
#endif

6
arch/arm/kernel/hw_breakpoint.c
View File

@ -966,7 +966,7 @@ static void reset_ctrl_regs(void *unused)
}
if (err) {
pr_warning("CPU %d debug is powered down!\n", cpu);
pr_warn_once("CPU %d debug is powered down!\n", cpu);
cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
return;
}
@ -987,7 +987,7 @@ clear_vcr:
isb();
if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
pr_warning("CPU %d failed to disable vector catch\n", cpu);
pr_warn_once("CPU %d failed to disable vector catch\n", cpu);
return;
}
@ -1007,7 +1007,7 @@ clear_vcr:
}
if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
pr_warning("CPU %d failed to clear debug register pairs\n", cpu);
pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu);
return;
}

24
arch/arm/kernel/setup.c
View File

@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
printk("%s", buf);
}
static void __init cpuid_init_hwcaps(void)
{
unsigned int divide_instrs;
if (cpu_architecture() < CPU_ARCH_ARMv7)
return;
divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
switch (divide_instrs) {
case 2:
elf_hwcap |= HWCAP_IDIVA;
case 1:
elf_hwcap |= HWCAP_IDIVT;
}
}
static void __init feat_v6_fixup(void)
{
int id = read_cpuid_id();
@ -483,8 +500,11 @@ static void __init setup_processor(void)
snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
list->elf_name, ENDIANNESS);
elf_hwcap = list->elf_hwcap;
cpuid_init_hwcaps();
#ifndef CONFIG_ARM_THUMB
elf_hwcap &= ~HWCAP_THUMB;
elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
#endif
feat_v6_fixup();
@ -524,7 +544,7 @@ int __init arm_add_memory(phys_addr_t start, phys_addr_t size)
size -= start & ~PAGE_MASK;
bank->start = PAGE_ALIGN(start);
#ifndef CONFIG_LPAE
#ifndef CONFIG_ARM_LPAE
if (bank->start + size < bank->start) {
printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
"32-bit physical address space\n", (long long)start);

5
arch/arm/kernel/smp.c
View File

@ -480,7 +480,7 @@ static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
evt->features = CLOCK_EVT_FEAT_ONESHOT |
CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_DUMMY;
evt->rating = 400;
evt->rating = 100;
evt->mult = 1;
evt->set_mode = broadcast_timer_set_mode;
@ -673,9 +673,6 @@ static int cpufreq_callback(struct notifier_block *nb,
if (freq->flags & CPUFREQ_CONST_LOOPS)
return NOTIFY_OK;
if (arm_delay_ops.const_clock)
return NOTIFY_OK;
if (!per_cpu(l_p_j_ref, cpu)) {
per_cpu(l_p_j_ref, cpu) =
per_cpu(cpu_data, cpu).loops_per_jiffy;

66
arch/arm/kernel/smp_tlb.c
View File

@ -12,6 +12,7 @@
#include <asm/smp_plat.h>
#include <asm/tlbflush.h>
#include <asm/mmu_context.h>
/**********************************************************************/
@ -69,12 +70,72 @@ static inline void ipi_flush_bp_all(void *ignored)
local_flush_bp_all();
}
#ifdef CONFIG_ARM_ERRATA_798181
static int erratum_a15_798181(void)
{
unsigned int midr = read_cpuid_id();
/* Cortex-A15 r0p0..r3p2 affected */
if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2)
return 0;
return 1;
}
#else
static int erratum_a15_798181(void)
{
return 0;
}
#endif
static void ipi_flush_tlb_a15_erratum(void *arg)
{
dmb();
}
static void broadcast_tlb_a15_erratum(void)
{
if (!erratum_a15_798181())
return;
dummy_flush_tlb_a15_erratum();
smp_call_function_many(cpu_online_mask, ipi_flush_tlb_a15_erratum,
NULL, 1);
}
static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
{
int cpu;
cpumask_t mask = { CPU_BITS_NONE };
if (!erratum_a15_798181())
return;
dummy_flush_tlb_a15_erratum();
for_each_online_cpu(cpu) {
if (cpu == smp_processor_id())
continue;
/*
* We only need to send an IPI if the other CPUs are running
* the same ASID as the one being invalidated. There is no
* need for locking around the active_asids check since the
* switch_mm() function has at least one dmb() (as required by
* this workaround) in case a context switch happens on
* another CPU after the condition below.
*/
if (atomic64_read(&mm->context.id) ==
atomic64_read(&per_cpu(active_asids, cpu)))
cpumask_set_cpu(cpu, &mask);
}
smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
}
void flush_tlb_all(void)
{
if (tlb_ops_need_broadcast())
on_each_cpu(ipi_flush_tlb_all, NULL, 1);
else
local_flush_tlb_all();
broadcast_tlb_a15_erratum();
}
void flush_tlb_mm(struct mm_struct *mm)
@ -83,6 +144,7 @@ void flush_tlb_mm(struct mm_struct *mm)
on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1);
else
local_flush_tlb_mm(mm);
broadcast_tlb_mm_a15_erratum(mm);
}
void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
@ -95,6 +157,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
&ta, 1);
} else
local_flush_tlb_page(vma, uaddr);
broadcast_tlb_mm_a15_erratum(vma->vm_mm);
}
void flush_tlb_kernel_page(unsigned long kaddr)
@ -105,6 +168,7 @@ void flush_tlb_kernel_page(unsigned long kaddr)
on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
} else
local_flush_tlb_kernel_page(kaddr);
broadcast_tlb_a15_erratum();
}
void flush_tlb_range(struct vm_area_struct *vma,
@ -119,6 +183,7 @@ void flush_tlb_range(struct vm_area_struct *vma,
&ta, 1);
} else
local_flush_tlb_range(vma, start, end);
broadcast_tlb_mm_a15_erratum(vma->vm_mm);
}
void flush_tlb_kernel_range(unsigned long start, unsigned long end)
@ -130,6 +195,7 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end)
on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
} else
local_flush_tlb_kernel_range(start, end);
broadcast_tlb_a15_erratum();
}
void flush_bp_all(void)

35
arch/arm/kvm/vgic.c
View File

@ -883,8 +883,7 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
lr, irq, vgic_cpu->vgic_lr[lr]);
BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
goto out;
return true;
}
/* Try to use another LR for this interrupt */
@ -898,7 +897,6 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
vgic_cpu->vgic_irq_lr_map[irq] = lr;
set_bit(lr, vgic_cpu->lr_used);
out:
if (!vgic_irq_is_edge(vcpu, irq))
vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;
@ -1018,21 +1016,6 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr);
/*
* We do not need to take the distributor lock here, since the only
* action we perform is clearing the irq_active_bit for an EOIed
* level interrupt. There is a potential race with
* the queuing of an interrupt in __kvm_vgic_flush_hwstate(), where we
* check if the interrupt is already active. Two possibilities:
*
* - The queuing is occurring on the same vcpu: cannot happen,
* as we're already in the context of this vcpu, and
* executing the handler
* - The interrupt has been migrated to another vcpu, and we
* ignore this interrupt for this run. Big deal. It is still
* pending though, and will get considered when this vcpu
* exits.
*/
if (vgic_cpu->vgic_misr & GICH_MISR_EOI) {
/*
* Some level interrupts have been EOIed. Clear their
@ -1054,6 +1037,13 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
} else {
vgic_cpu_irq_clear(vcpu, irq);
}
/*
* Despite being EOIed, the LR may not have
* been marked as empty.
*/
set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr);
vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT;
}
}
@ -1064,9 +1054,8 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
}
/*
* Sync back the VGIC state after a guest run. We do not really touch
* the distributor here (the irq_pending_on_cpu bit is safe to set),
* so there is no need for taking its lock.
* Sync back the VGIC state after a guest run. The distributor lock is
* needed so we don't get preempted in the middle of the state processing.
*/
static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
{
@ -1112,10 +1101,14 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
{
struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
if (!irqchip_in_kernel(vcpu->kvm))
return;
spin_lock(&dist->lock);
__kvm_vgic_sync_hwstate(vcpu);
spin_unlock(&dist->lock);
}
int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)

8
arch/arm/lib/delay.c
View File

@ -58,7 +58,7 @@ static void __timer_delay(unsigned long cycles)
static void __timer_const_udelay(unsigned long xloops)
{
unsigned long long loops = xloops;
loops *= loops_per_jiffy;
loops *= arm_delay_ops.ticks_per_jiffy;
__timer_delay(loops >> UDELAY_SHIFT);
}
@ -73,11 +73,13 @@ void __init register_current_timer_delay(const struct delay_timer *timer)
pr_info("Switching to timer-based delay loop\n");
delay_timer = timer;
lpj_fine = timer->freq / HZ;
loops_per_jiffy = lpj_fine;
/* cpufreq may scale loops_per_jiffy, so keep a private copy */
arm_delay_ops.ticks_per_jiffy = lpj_fine;
arm_delay_ops.delay = __timer_delay;
arm_delay_ops.const_udelay = __timer_const_udelay;
arm_delay_ops.udelay = __timer_udelay;
arm_delay_ops.const_clock = true;
delay_calibrated = true;
} else {
pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");

33
arch/arm/lib/memset.S
View File

@ -14,31 +14,15 @@
.text
.align 5
.word 0
1: subs r2, r2, #4 @ 1 do we have enough
blt 5f @ 1 bytes to align with?
cmp r3, #2 @ 1
strltb r1, [ip], #1 @ 1
strleb r1, [ip], #1 @ 1
strb r1, [ip], #1 @ 1
add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
/*
* The pointer is now aligned and the length is adjusted. Try doing the
* memset again.
*/
ENTRY(memset)
/*
* Preserve the contents of r0 for the return value.
*/
mov ip, r0
ands r3, ip, #3 @ 1 unaligned?
bne 1b @ 1
ands r3, r0, #3 @ 1 unaligned?
mov ip, r0 @ preserve r0 as return value
bne 6f @ 1
/*
* we know that the pointer in ip is aligned to a word boundary.
*/
orr r1, r1, r1, lsl #8
1: orr r1, r1, r1, lsl #8
orr r1, r1, r1, lsl #16
mov r3, r1
cmp r2, #16
@ -127,4 +111,13 @@ ENTRY(memset)
tst r2, #1
strneb r1, [ip], #1
mov pc, lr
6: subs r2, r2, #4 @ 1 do we have enough
blt 5b @ 1 bytes to align with?
cmp r3, #2 @ 1
strltb r1, [ip], #1 @ 1
strleb r1, [ip], #1 @ 1
strb r1, [ip], #1 @ 1
add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
b 1b
ENDPROC(memset)

1
arch/arm/mach-at91/board-foxg20.c
View File

@ -176,6 +176,7 @@ static struct w1_gpio_platform_data w1_gpio_pdata = {
/* If you choose to use a pin other than PB16 it needs to be 3.3V */
.pin = AT91_PIN_PB16,
.is_open_drain = 1,
.ext_pullup_enable_pin = -EINVAL,
};
static struct platform_device w1_device = {

1
arch/arm/mach-at91/board-stamp9g20.c
View File

@ -188,6 +188,7 @@ static struct spi_board_info portuxg20_spi_devices[] = {
static struct w1_gpio_platform_data w1_gpio_pdata = {
.pin = AT91_PIN_PA29,
.is_open_drain = 1,
.ext_pullup_enable_pin = -EINVAL,
};
static struct platform_device w1_device = {

8
arch/arm/mach-at91/include/mach/gpio.h
View File

@ -209,6 +209,14 @@ extern int at91_get_gpio_value(unsigned pin);
extern void at91_gpio_suspend(void);
extern void at91_gpio_resume(void);
#ifdef CONFIG_PINCTRL_AT91
extern void at91_pinctrl_gpio_suspend(void);
extern void at91_pinctrl_gpio_resume(void);
#else
static inline void at91_pinctrl_gpio_suspend(void) {}
static inline void at91_pinctrl_gpio_resume(void) {}
#endif
#endif /* __ASSEMBLY__ */
#endif

20
arch/arm/mach-at91/irq.c
View File

@ -92,23 +92,21 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value)
void at91_irq_suspend(void)
{
int i = 0, bit;
int bit = -1;
if (has_aic5()) {
/* disable enabled irqs */
while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
at91_aic_write(AT91_AIC5_SSR,
bit & AT91_AIC5_INTSEL_MSK);
at91_aic_write(AT91_AIC5_IDCR, 1);
i = bit;
}
/* enable wakeup irqs */
i = 0;
while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
bit = -1;
while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
at91_aic_write(AT91_AIC5_SSR,
bit & AT91_AIC5_INTSEL_MSK);
at91_aic_write(AT91_AIC5_IECR, 1);
i = bit;
}
} else {
at91_aic_write(AT91_AIC_IDCR, *backups);
@ -118,23 +116,21 @@ void at91_irq_suspend(void)
void at91_irq_resume(void)
{
int i = 0, bit;
int bit = -1;
if (has_aic5()) {
/* disable wakeup irqs */
while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
at91_aic_write(AT91_AIC5_SSR,
bit & AT91_AIC5_INTSEL_MSK);
at91_aic_write(AT91_AIC5_IDCR, 1);
i = bit;
}
/* enable irqs disabled for suspend */
i = 0;
while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
bit = -1;
while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
at91_aic_write(AT91_AIC5_SSR,
bit & AT91_AIC5_INTSEL_MSK);
at91_aic_write(AT91_AIC5_IECR, 1);
i = bit;
}
} else {
at91_aic_write(AT91_AIC_IDCR, *wakeups);

Some files were not shown because too many files have changed in this diff Show More