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drm/i915/tgl: WaDisableGPGPUMidThreadPreemption 

Enable FtrPerCtxtPreemptionGranularityControl bit and select thread-
group as the default preemption level.

v2:
 * Remove register whitelisting (Rafael, Tony).

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: piotr.zdunowski@intel.com
Cc: michal.mrozek@intel.com
Cc: Tony Ye <tony.ye@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Acked-by: Rafael Antognolli <rafael.antognolli@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Tony Ye <tony.ye@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200304153144.10675-1-tvrtko.ursulin@linux.intel.com
This commit is contained in:
Tvrtko Ursulin 2020-03-04 15:31:44 +00:00
parent be90e34483
commit 9b11bbf0c4
1 changed files with 7 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/drm/i915/gt/intel_workarounds.c
View File

@ -601,6 +601,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
*/ */
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
FF_MODE2_TDS_TIMER_128, 0); FF_MODE2_TDS_TIMER_128, 0);
/* WaDisableGPGPUMidThreadPreemption:tgl */
WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
GEN9_PREEMPT_GPGPU_LEVEL_MASK,
GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
} }
static void static void
@ -1475,8 +1480,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
PSDUNIT_CLKGATE_DIS); PSDUNIT_CLKGATE_DIS);
} }
if (IS_GEN_RANGE(i915, 9, 11)) { if (IS_GEN_RANGE(i915, 9, 12)) {
/* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */ /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
wa_masked_en(wal, wa_masked_en(wal,
GEN7_FF_SLICE_CS_CHICKEN1, GEN7_FF_SLICE_CS_CHICKEN1,
GEN9_FFSC_PERCTX_PREEMPT_CTRL); GEN9_FFSC_PERCTX_PREEMPT_CTRL);