drm/i915/gen9: Add WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken
In Indirect context w/a batch buffer, +WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken v2: SKL revision id was used for BXT, copy paste error found during internal review (Bob Beckett). v3: explain why part of the WA is in Per ctx batch (Mika) Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1292,6 +1292,16 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
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struct drm_device *dev = ring->dev;
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uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
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/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
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if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
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(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
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wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
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wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
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wa_ctx_emit(batch, index,
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_MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
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wa_ctx_emit(batch, index, MI_NOOP);
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}
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/* WaDisableCtxRestoreArbitration:skl,bxt */
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if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
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(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
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@ -946,8 +946,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
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/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
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WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
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GEN9_RHWO_OPTIMIZATION_DISABLE);
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WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
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DISABLE_PIXEL_MASK_CAMMING);
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/*
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* WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
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* but we do that in per ctx batchbuffer as there is an issue
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* with this register not getting restored on ctx restore
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*/
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}
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if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
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