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dt-bindings: riscv: Fix CPU schema errors 

Fix the errors in the RiscV CPU DT schema:

Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property

The DT spec allows for 'timebase-frequency' to be in 'cpu' or 'cpus' node
and RiscV requires it in /cpus node, so make it disallowed in cpu
nodes.

Fixes: 4fd669a8c4 ("dt-bindings: riscv: convert cpu binding to json-schema")
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org
Acked-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Rob Herring 2019-09-24 14:37:56 -05:00
parent f437ade329
commit 9af865d95b
1 changed files with 13 additions and 16 deletions
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13
Documentation/devicetree/bindings/riscv/cpus.yaml
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@ -24,7 +24,8 @@ description: |
properties: properties:
compatible: compatible:
items: oneOf:
- items:
- enum: - enum:
- sifive,rocket0 - sifive,rocket0
- sifive,e5 - sifive,e5
@ -33,6 +34,7 @@ properties:
- sifive,u54 - sifive,u54
- sifive,u5 - sifive,u5
- const: riscv - const: riscv
- const: riscv # Simulator only
description: description:
Identifies that the hart uses the RISC-V instruction set Identifies that the hart uses the RISC-V instruction set
and identifies the type of the hart. and identifies the type of the hart.
@ -66,12 +68,8 @@ properties:
insensitive, letters in the riscv,isa string must be all insensitive, letters in the riscv,isa string must be all
lowercase to simplify parsing. lowercase to simplify parsing.
timebase-frequency: # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
type: integer timebase-frequency: false
minimum: 1
description:
Specifies the clock frequency of the system timer in Hz.
This value is common to all harts on a single system image.
interrupt-controller: interrupt-controller:
type: object type: object
@ -93,7 +91,6 @@ properties:
required: required:
- riscv,isa - riscv,isa
- timebase-frequency
- interrupt-controller - interrupt-controller
examples: examples: