dpaa_eth: add support for DPAA Ethernet
This introduces the Freescale Data Path Acceleration Architecture (DPAA) Ethernet driver (dpaa_eth) that builds upon the DPAA QMan, BMan, PAMU and FMan drivers to deliver Ethernet connectivity on the Freescale DPAA QorIQ platforms. Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Madalin Bucur
David S. Miller
parent
ff86aae3b4
commit
9ad1a37493
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@ -93,4 +93,6 @@ config GIANFAR
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and MPC86xx family of chips, the eTSEC on LS1021A and the FEC
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on the 8540.
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source "drivers/net/ethernet/freescale/dpaa/Kconfig"
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endif # NET_VENDOR_FREESCALE
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@ -22,3 +22,4 @@ obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
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ucc_geth_driver-objs := ucc_geth.o ucc_geth_ethtool.o
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obj-$(CONFIG_FSL_FMAN) += fman/
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obj-$(CONFIG_FSL_DPAA_ETH) += dpaa/
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@ -0,0 +1,10 @@
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menuconfig FSL_DPAA_ETH
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tristate "DPAA Ethernet"
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depends on FSL_SOC && FSL_DPAA && FSL_FMAN
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select PHYLIB
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select FSL_FMAN_MAC
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---help---
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Data Path Acceleration Architecture Ethernet driver,
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supporting the Freescale QorIQ chips.
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Depends on Freescale Buffer Manager and Queue Manager
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driver and Frame Manager Driver.
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@ -0,0 +1,11 @@
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#
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# Makefile for the Freescale DPAA Ethernet controllers
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#
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# Include FMan headers
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FMAN = $(srctree)/drivers/net/ethernet/freescale/fman
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ccflags-y += -I$(FMAN)
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obj-$(CONFIG_FSL_DPAA_ETH) += fsl_dpa.o
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fsl_dpa-objs += dpaa_eth.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,144 @@
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/* Copyright 2008 - 2016 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DPAA_H
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#define __DPAA_H
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#include <linux/netdevice.h>
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#include <soc/fsl/qman.h>
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#include <soc/fsl/bman.h>
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#include "fman.h"
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#include "mac.h"
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#define DPAA_ETH_TXQ_NUM NR_CPUS
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#define DPAA_BPS_NUM 3 /* number of bpools per interface */
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/* More detailed FQ types - used for fine-grained WQ assignments */
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enum dpaa_fq_type {
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FQ_TYPE_RX_DEFAULT = 1, /* Rx Default FQs */
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FQ_TYPE_RX_ERROR, /* Rx Error FQs */
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FQ_TYPE_TX, /* "Real" Tx FQs */
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FQ_TYPE_TX_CONFIRM, /* Tx default Conf FQ (actually an Rx FQ) */
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FQ_TYPE_TX_CONF_MQ, /* Tx conf FQs (one for each Tx FQ) */
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FQ_TYPE_TX_ERROR, /* Tx Error FQs (these are actually Rx FQs) */
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};
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struct dpaa_fq {
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struct qman_fq fq_base;
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struct list_head list;
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struct net_device *net_dev;
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bool init;
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u32 fqid;
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u32 flags;
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u16 channel;
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u8 wq;
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enum dpaa_fq_type fq_type;
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};
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struct dpaa_fq_cbs {
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struct qman_fq rx_defq;
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struct qman_fq tx_defq;
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struct qman_fq rx_errq;
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struct qman_fq tx_errq;
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struct qman_fq egress_ern;
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};
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struct dpaa_bp {
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/* device used in the DMA mapping operations */
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struct device *dev;
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/* current number of buffers in the buffer pool alloted to each CPU */
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int __percpu *percpu_count;
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/* all buffers allocated for this pool have this raw size */
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size_t raw_size;
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/* all buffers in this pool have this same usable size */
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size_t size;
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/* the buffer pools are initialized with config_count buffers for each
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* CPU; at runtime the number of buffers per CPU is constantly brought
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* back to this level
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*/
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u16 config_count;
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u8 bpid;
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struct bman_pool *pool;
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/* bpool can be seeded before use by this cb */
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int (*seed_cb)(struct dpaa_bp *);
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/* bpool can be emptied before freeing by this cb */
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void (*free_buf_cb)(const struct dpaa_bp *, struct bm_buffer *);
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atomic_t refs;
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};
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struct dpaa_napi_portal {
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struct napi_struct napi;
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struct qman_portal *p;
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bool down;
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};
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struct dpaa_percpu_priv {
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struct net_device *net_dev;
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struct dpaa_napi_portal np;
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struct rtnl_link_stats64 stats;
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};
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struct dpaa_buffer_layout {
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u16 priv_data_size;
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};
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struct dpaa_priv {
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struct dpaa_percpu_priv __percpu *percpu_priv;
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struct dpaa_bp *dpaa_bps[DPAA_BPS_NUM];
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/* Store here the needed Tx headroom for convenience and speed
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* (even though it can be computed based on the fields of buf_layout)
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*/
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u16 tx_headroom;
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struct net_device *net_dev;
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struct mac_device *mac_dev;
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struct qman_fq *egress_fqs[DPAA_ETH_TXQ_NUM];
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struct qman_fq *conf_fqs[DPAA_ETH_TXQ_NUM];
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u16 channel;
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struct list_head dpaa_fq_list;
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u32 msg_enable; /* net_device message level */
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struct {
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/* All egress queues to a given net device belong to one
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* (and the same) congestion group.
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*/
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struct qman_cgr cgr;
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} cgr_data;
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/* Use a per-port CGR for ingress traffic. */
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bool use_ingress_cgr;
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struct qman_cgr ingress_cgr;
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struct dpaa_buffer_layout buf_layout[2];
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u16 rx_headroom;
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};
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#endif /* __DPAA_H */
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