ARM: zynq: add support for ARCH_MULTIPLATFORM
The majority of changes are necessary to remove dependencies on header
files within arch/arm/mach-zynq/include/mach:
uncompress.h
- Deleted. It is unused for ARCH_MULTIPLATFORM builds.
uart.h:
- Move uart definitions out of uart.h into debug/zynq.S, which is
now the only user
zynq_soc.h:
- Move SCU address definitions into common.c.
- Other #defines, such as PERIPHERAL_CLOCK_RATE, TTC0_BASE, etc, are
unused and can be dropped
Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Josh Cartwright
Michal Simek
parent
385f02b169
commit
9a45eb691d
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@ -955,18 +955,6 @@ config ARCH_VT8500
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help
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Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
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config ARCH_ZYNQ
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bool "Xilinx Zynq ARM Cortex A9 Platform"
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select ARM_AMBA
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select ARM_GIC
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select COMMON_CLK
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select CPU_V7
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select GENERIC_CLOCKEVENTS
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select ICST
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select MIGHT_HAVE_CACHE_L2X0
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select USE_OF
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help
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Support for Xilinx Zynq ARM Cortex A9 Platform
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endchoice
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menu "Multiple platform selection"
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@ -1128,6 +1116,8 @@ source "arch/arm/plat-versatile/Kconfig"
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source "arch/arm/mach-w90x900/Kconfig"
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source "arch/arm/mach-zynq/Kconfig"
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# Definitions to make life easier
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config ARCH_ACORN
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bool
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@ -12,9 +12,25 @@
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
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#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
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#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
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#include <mach/zynq_soc.h>
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#include <mach/uart.h>
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#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
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#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
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#define UART0_PHYS 0xE0000000
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#define UART1_PHYS 0xE0001000
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#define UART_SIZE SZ_4K
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#define UART_VIRT 0xF0001000
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#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
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# define LL_UART_PADDR UART1_PHYS
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#else
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# define LL_UART_PADDR UART0_PHYS
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#endif
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#define LL_UART_VADDR UART_VIRT
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.macro addruart, rp, rv, tmp
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ldr \rp, =LL_UART_PADDR @ physical
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@ -0,0 +1,13 @@
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config ARCH_ZYNQ
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bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
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select ARM_AMBA
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select ARM_GIC
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select COMMON_CLK
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select CPU_V7
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select GENERIC_CLOCKEVENTS
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select ICST
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select MIGHT_HAVE_CACHE_L2X0
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select USE_OF
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select SPARSE_IRQ
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help
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Support for Xilinx Zynq ARM Cortex A9 Platform
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@ -30,10 +30,10 @@
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#include <asm/mach/time.h>
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#include <asm/mach-types.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <mach/zynq_soc.h>
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#include "common.h"
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static struct of_device_id zynq_of_bus_ids[] __initdata = {
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@ -68,9 +68,9 @@ static void __init xilinx_irq_init(void)
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of_irq_init(irq_match);
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}
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/* The minimum devices needed to be mapped before the VM system is up and
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* running include the GIC, UART and Timer Counter.
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*/
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#define SCU_PERIPH_PHYS 0xF8F00000
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#define SCU_PERIPH_SIZE SZ_8K
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#define SCU_PERIPH_VIRT (VMALLOC_END - SCU_PERIPH_SIZE)
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static struct map_desc scu_desc __initdata = {
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.virtual = SCU_PERIPH_VIRT,
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@ -1,25 +0,0 @@
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/* arch/arm/mach-zynq/include/mach/uart.h
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*
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* Copyright (C) 2011 Xilinx
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MACH_UART_H__
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#define __MACH_UART_H__
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#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
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#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
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#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
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#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
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#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
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#endif
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@ -1,51 +0,0 @@
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/* arch/arm/mach-zynq/include/mach/uncompress.h
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*
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* Copyright (C) 2011 Xilinx
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MACH_UNCOMPRESS_H__
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#define __MACH_UNCOMPRESS_H__
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#include <linux/io.h>
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#include <asm/processor.h>
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#include <mach/zynq_soc.h>
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#include <mach/uart.h>
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void arch_decomp_setup(void)
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{
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}
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static inline void flush(void)
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{
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/*
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* Wait while the FIFO is not empty
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*/
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while (!(__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) &
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UART_SR_TXEMPTY))
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cpu_relax();
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}
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#define arch_decomp_wdog()
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static void putc(char ch)
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{
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/*
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* Wait for room in the FIFO, then write the char into the FIFO
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*/
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while (__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) &
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UART_SR_TXFULL)
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cpu_relax();
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__raw_writel(ch, IOMEM(LL_UART_PADDR + UART_FIFO_OFFSET));
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}
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#endif
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@ -1,49 +0,0 @@
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/* arch/arm/mach-zynq/include/mach/zynq_soc.h
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*
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* Copyright (C) 2011 Xilinx
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MACH_XILINX_SOC_H__
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#define __MACH_XILINX_SOC_H__
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#include <asm/pgtable.h>
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#define PERIPHERAL_CLOCK_RATE 2500000
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/* Static peripheral mappings are mapped at the top of the vmalloc region. The
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* early uart mapping causes intermediate problems/failure at certain
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* addresses, including the very top of the vmalloc region. Map it at an
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* address that is known to work.
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*/
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#define UART0_PHYS 0xE0000000
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#define UART1_PHYS 0xE0001000
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#define UART_SIZE SZ_4K
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#define UART_VIRT 0xF0001000
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#define SCU_PERIPH_PHYS 0xF8F00000
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#define SCU_PERIPH_SIZE SZ_8K
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#define SCU_PERIPH_VIRT (VMALLOC_END - SCU_PERIPH_SIZE)
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#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
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# define LL_UART_PADDR UART1_PHYS
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#else
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# define LL_UART_PADDR UART0_PHYS
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#endif
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#define LL_UART_VADDR UART_VIRT
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/* The following are intended for the devices that are mapped early */
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#define TTC0_BASE IOMEM(TTC0_VIRT)
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#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT)
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#endif
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