forcedeth: add tx pause limit
This patch adds support for limiting the number of tx pause frames to a default of 8. Previously, hardware would send out continuous stream of pause frames. Signed-off-by: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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06941931d8
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@ -249,6 +249,8 @@ enum {
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#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
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#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
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#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
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NvRegTxPauseFrameLimit = 0x174,
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#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
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NvRegMIIStatus = 0x180,
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#define NVREG_MIISTAT_ERROR 0x0001
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#define NVREG_MIISTAT_LINKCHANGE 0x0008
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@ -3076,8 +3078,11 @@ static void nv_update_pause(struct net_device *dev, u32 pause_flags)
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u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
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if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
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pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
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if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)
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if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
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pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
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/* limit the number of tx pause frames to a default of 8 */
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writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
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}
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writel(pause_enable, base + NvRegTxPauseFrame);
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writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
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np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
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