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drm/msm/a6xx: Add support for A640 speed binning 

Add support for matching QFPROM fuse values to get the correct speed bin
on A640 (SM8150) GPUs.

Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/530042/
Link: https://lore.kernel.org/r/20230331-topic-konahana_speedbin-v3-1-2dede22dd7f7@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Konrad Dybcio 2023-03-31 03:14:49 +02:00 committed by Rob Clark
parent 780668dfef
commit 9a06cd9a0f
1 changed files with 13 additions and 0 deletions
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13
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
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@ -1837,6 +1837,16 @@ static u32 a619_get_speed_bin(u32 fuse)
return UINT_MAX;
}
static u32 a640_get_speed_bin(u32 fuse)
{
if (fuse == 0)
return 0;
else if (fuse == 1)
return 1;
return UINT_MAX;
}
static u32 adreno_7c3_get_speed_bin(u32 fuse)
{
if (fuse == 0)
@ -1862,6 +1872,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
val = adreno_7c3_get_speed_bin(fuse);
if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
val = a640_get_speed_bin(fuse);
if (val == UINT_MAX) {
DRM_DEV_ERROR(dev,
"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",