!249 Backport pseudo NMI for PMU
Merge pull request !249 from lcy/devel-35
This commit is contained in:
chinaljp030
Gitee
commit
9a02555d16
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@ -372,6 +372,73 @@ static inline bool armv8pmu_event_is_chained(struct perf_event *event)
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#define ARMV8_IDX_TO_COUNTER(x) \
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(((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
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/*
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* This code is really good
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*/
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#define PMEVN_CASE(n, case_macro) \
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case n: case_macro(n); break
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#define PMEVN_SWITCH(x, case_macro) \
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do { \
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switch (x) { \
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PMEVN_CASE(0, case_macro); \
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PMEVN_CASE(1, case_macro); \
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PMEVN_CASE(2, case_macro); \
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PMEVN_CASE(3, case_macro); \
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PMEVN_CASE(4, case_macro); \
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PMEVN_CASE(5, case_macro); \
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PMEVN_CASE(6, case_macro); \
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PMEVN_CASE(7, case_macro); \
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PMEVN_CASE(8, case_macro); \
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PMEVN_CASE(9, case_macro); \
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PMEVN_CASE(10, case_macro); \
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PMEVN_CASE(11, case_macro); \
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PMEVN_CASE(12, case_macro); \
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PMEVN_CASE(13, case_macro); \
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PMEVN_CASE(14, case_macro); \
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PMEVN_CASE(15, case_macro); \
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PMEVN_CASE(16, case_macro); \
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PMEVN_CASE(17, case_macro); \
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PMEVN_CASE(18, case_macro); \
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PMEVN_CASE(19, case_macro); \
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PMEVN_CASE(20, case_macro); \
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PMEVN_CASE(21, case_macro); \
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PMEVN_CASE(22, case_macro); \
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PMEVN_CASE(23, case_macro); \
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PMEVN_CASE(24, case_macro); \
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PMEVN_CASE(25, case_macro); \
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PMEVN_CASE(26, case_macro); \
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PMEVN_CASE(27, case_macro); \
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PMEVN_CASE(28, case_macro); \
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PMEVN_CASE(29, case_macro); \
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PMEVN_CASE(30, case_macro); \
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default: WARN(1, "Invalid PMEV* index\n"); \
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} \
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} while (0)
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#define RETURN_READ_PMEVCNTRN(n) \
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return read_sysreg(pmevcntr##n##_el0)
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static unsigned long read_pmevcntrn(int n)
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{
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PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
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return 0;
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}
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#define WRITE_PMEVCNTRN(n) \
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write_sysreg(val, pmevcntr##n##_el0)
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static void write_pmevcntrn(int n, unsigned long val)
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{
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PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
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}
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#define WRITE_PMEVTYPERN(n) \
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write_sysreg(val, pmevtyper##n##_el0)
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static void write_pmevtypern(int n, unsigned long val)
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{
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PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
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}
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static inline u32 armv8pmu_pmcr_read(void)
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{
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return read_sysreg(pmcr_el0);
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@ -400,17 +467,11 @@ static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
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return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
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}
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static inline void armv8pmu_select_counter(int idx)
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{
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u32 counter = ARMV8_IDX_TO_COUNTER(idx);
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write_sysreg(counter, pmselr_el0);
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isb();
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}
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static inline u32 armv8pmu_read_evcntr(int idx)
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{
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armv8pmu_select_counter(idx);
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return read_sysreg(pmxevcntr_el0);
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u32 counter = ARMV8_IDX_TO_COUNTER(idx);
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return read_pmevcntrn(counter);
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}
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static inline u64 armv8pmu_read_hw_counter(struct perf_event *event)
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@ -444,8 +505,9 @@ static u64 armv8pmu_read_counter(struct perf_event *event)
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static inline void armv8pmu_write_evcntr(int idx, u32 value)
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{
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armv8pmu_select_counter(idx);
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write_sysreg(value, pmxevcntr_el0);
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u32 counter = ARMV8_IDX_TO_COUNTER(idx);
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write_pmevcntrn(counter, value);
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}
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static inline void armv8pmu_write_hw_counter(struct perf_event *event,
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@ -486,9 +548,10 @@ static void armv8pmu_write_counter(struct perf_event *event, u64 value)
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static inline void armv8pmu_write_evtype(int idx, u32 val)
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{
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armv8pmu_select_counter(idx);
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u32 counter = ARMV8_IDX_TO_COUNTER(idx);
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val &= ARMV8_PMU_EVTYPE_MASK;
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write_sysreg(val, pmxevtyper_el0);
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write_pmevtypern(counter, val);
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}
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static inline void armv8pmu_write_event_type(struct perf_event *event)
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@ -508,6 +571,9 @@ static inline void armv8pmu_write_event_type(struct perf_event *event)
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armv8pmu_write_evtype(idx - 1, hwc->config_base);
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armv8pmu_write_evtype(idx, chain_evt);
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} else {
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if (idx == ARMV8_IDX_CYCLE_COUNTER)
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write_sysreg(hwc->config_base, pmccfiltr_el0);
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else
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armv8pmu_write_evtype(idx, hwc->config_base);
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}
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}
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@ -515,6 +581,11 @@ static inline void armv8pmu_write_event_type(struct perf_event *event)
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static inline int armv8pmu_enable_counter(int idx)
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{
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u32 counter = ARMV8_IDX_TO_COUNTER(idx);
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/*
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* Make sure event configuration register writes are visible before we
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* enable the counter.
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* */
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isb();
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write_sysreg(BIT(counter), pmcntenset_el0);
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return idx;
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}
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@ -542,6 +613,11 @@ static inline int armv8pmu_disable_counter(int idx)
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{
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u32 counter = ARMV8_IDX_TO_COUNTER(idx);
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write_sysreg(BIT(counter), pmcntenclr_el0);
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/*
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* Make sure the effects of disabling the counter are visible before we
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* start configuring the event.
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*/
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isb();
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return idx;
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}
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@ -610,15 +686,10 @@ static inline u32 armv8pmu_getreset_flags(void)
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static void armv8pmu_enable_event(struct perf_event *event)
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{
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unsigned long flags;
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struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
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struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
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/*
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* Enable counter and interrupt, and set the counter to count
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* the event that we're interested in.
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*/
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raw_spin_lock_irqsave(&events->pmu_lock, flags);
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/*
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* Disable counter
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@ -626,7 +697,7 @@ static void armv8pmu_enable_event(struct perf_event *event)
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armv8pmu_disable_event_counter(event);
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/*
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* Set event (if destined for PMNx counters).
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* Set event.
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*/
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armv8pmu_write_event_type(event);
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@ -639,21 +710,10 @@ static void armv8pmu_enable_event(struct perf_event *event)
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* Enable counter
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*/
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armv8pmu_enable_event_counter(event);
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raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
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}
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static void armv8pmu_disable_event(struct perf_event *event)
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{
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unsigned long flags;
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struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
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struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
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/*
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* Disable counter and interrupt
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*/
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raw_spin_lock_irqsave(&events->pmu_lock, flags);
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/*
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* Disable counter
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*/
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@ -663,30 +723,18 @@ static void armv8pmu_disable_event(struct perf_event *event)
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* Disable interrupt for this counter
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*/
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armv8pmu_disable_event_irq(event);
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raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
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}
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static void armv8pmu_start(struct arm_pmu *cpu_pmu)
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{
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unsigned long flags;
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struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
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raw_spin_lock_irqsave(&events->pmu_lock, flags);
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/* Enable all counters */
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armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
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raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
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}
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static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
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{
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unsigned long flags;
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struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
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raw_spin_lock_irqsave(&events->pmu_lock, flags);
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/* Disable all counters */
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armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
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raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
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}
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static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
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@ -739,20 +787,16 @@ static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
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if (!armpmu_event_set_period(event))
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continue;
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/*
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* Perf event overflow will queue the processing of the event as
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* an irq_work which will be taken care of in the handling of
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* IPI_IRQ_WORK.
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*/
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if (perf_event_overflow(event, &data, regs))
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cpu_pmu->disable(event);
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}
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armv8pmu_start(cpu_pmu);
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/*
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* Handle the pending perf events.
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*
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* Note: this call *must* be run with interrupts disabled. For
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* platforms that can have the PMU interrupts raised as an NMI, this
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* will not work.
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*/
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irq_work_run();
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return IRQ_HANDLED;
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}
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@ -26,8 +26,84 @@
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#include <asm/irq_regs.h>
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static int armpmu_count_irq_users(const int irq);
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struct pmu_irq_ops {
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void (*enable_pmuirq)(unsigned int irq);
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void (*disable_pmuirq)(unsigned int irq);
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void (*free_pmuirq)(unsigned int irq, int cpu, void __percpu *devid);
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};
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static void armpmu_free_pmuirq(unsigned int irq, int cpu, void __percpu *devid)
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{
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free_irq(irq, per_cpu_ptr(devid, cpu));
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}
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static const struct pmu_irq_ops pmuirq_ops = {
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.enable_pmuirq = enable_irq,
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.disable_pmuirq = disable_irq_nosync,
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.free_pmuirq = armpmu_free_pmuirq
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};
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static void armpmu_free_pmunmi(unsigned int irq, int cpu, void __percpu *devid)
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{
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free_nmi(irq, per_cpu_ptr(devid, cpu));
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}
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static const struct pmu_irq_ops pmunmi_ops = {
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.enable_pmuirq = enable_nmi,
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.disable_pmuirq = disable_nmi_nosync,
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.free_pmuirq = armpmu_free_pmunmi
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};
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static void armpmu_enable_percpu_pmuirq(unsigned int irq)
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{
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enable_percpu_irq(irq, IRQ_TYPE_NONE);
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}
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static void armpmu_free_percpu_pmuirq(unsigned int irq, int cpu,
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void __percpu *devid)
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{
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if (armpmu_count_irq_users(irq) == 1)
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free_percpu_irq(irq, devid);
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}
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static const struct pmu_irq_ops percpu_pmuirq_ops = {
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.enable_pmuirq = armpmu_enable_percpu_pmuirq,
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.disable_pmuirq = disable_percpu_irq,
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.free_pmuirq = armpmu_free_percpu_pmuirq
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};
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static void armpmu_enable_percpu_pmunmi(unsigned int irq)
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{
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if (!prepare_percpu_nmi(irq))
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enable_percpu_nmi(irq, IRQ_TYPE_NONE);
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}
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static void armpmu_disable_percpu_pmunmi(unsigned int irq)
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{
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disable_percpu_nmi(irq);
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teardown_percpu_nmi(irq);
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}
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static void armpmu_free_percpu_pmunmi(unsigned int irq, int cpu,
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void __percpu *devid)
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{
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if (armpmu_count_irq_users(irq) == 1)
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free_percpu_nmi(irq, devid);
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}
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static const struct pmu_irq_ops percpu_pmunmi_ops = {
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.enable_pmuirq = armpmu_enable_percpu_pmunmi,
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.disable_pmuirq = armpmu_disable_percpu_pmunmi,
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.free_pmuirq = armpmu_free_percpu_pmunmi
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};
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static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
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static DEFINE_PER_CPU(int, cpu_irq);
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static DEFINE_PER_CPU(const struct pmu_irq_ops *, cpu_irq_ops);
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static bool has_nmi;
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static inline u64 arm_pmu_event_max_period(struct perf_event *event)
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{
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@ -542,6 +618,23 @@ static int armpmu_count_irq_users(const int irq)
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return count;
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}
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static const struct pmu_irq_ops *armpmu_find_irq_ops(int irq)
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{
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const struct pmu_irq_ops *ops = NULL;
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int cpu;
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for_each_possible_cpu(cpu) {
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if (per_cpu(cpu_irq, cpu) != irq)
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continue;
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ops = per_cpu(cpu_irq_ops, cpu);
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if (ops)
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break;
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}
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return ops;
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}
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void armpmu_free_irq(int irq, int cpu)
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{
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if (per_cpu(cpu_irq, cpu) == 0)
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@ -549,18 +642,18 @@ void armpmu_free_irq(int irq, int cpu)
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if (WARN_ON(irq != per_cpu(cpu_irq, cpu)))
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return;
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if (!irq_is_percpu_devid(irq))
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free_irq(irq, per_cpu_ptr(&cpu_armpmu, cpu));
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else if (armpmu_count_irq_users(irq) == 1)
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free_percpu_irq(irq, &cpu_armpmu);
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per_cpu(cpu_irq_ops, cpu)->free_pmuirq(irq, cpu, &cpu_armpmu);
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per_cpu(cpu_irq, cpu) = 0;
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per_cpu(cpu_irq_ops, cpu) = NULL;
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}
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int armpmu_request_irq(int irq, int cpu)
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{
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int err = 0;
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const irq_handler_t handler = armpmu_dispatch_irq;
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const struct pmu_irq_ops *irq_ops;
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if (!irq)
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return 0;
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@ -580,17 +673,44 @@ int armpmu_request_irq(int irq, int cpu)
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IRQF_NO_THREAD;
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irq_set_status_flags(irq, IRQ_NOAUTOEN);
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err = request_nmi(irq, handler, irq_flags, "arm-pmu",
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per_cpu_ptr(&cpu_armpmu, cpu));
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/* If cannot get an NMI, get a normal interrupt */
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if (err) {
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err = request_irq(irq, handler, irq_flags, "arm-pmu",
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per_cpu_ptr(&cpu_armpmu, cpu));
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irq_ops = &pmuirq_ops;
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} else {
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has_nmi = true;
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irq_ops = &pmunmi_ops;
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}
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} else if (armpmu_count_irq_users(irq) == 0) {
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err = request_percpu_nmi(irq, handler, "arm-pmu", &cpu_armpmu);
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/* If cannot get an NMI, get a normal interrupt */
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if (err) {
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err = request_percpu_irq(irq, handler, "arm-pmu",
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&cpu_armpmu);
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irq_ops = &percpu_pmuirq_ops;
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} else {
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has_nmi= true;
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irq_ops = &percpu_pmunmi_ops;
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}
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} else {
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/* Per cpudevid irq was already requested by another CPU */
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irq_ops = armpmu_find_irq_ops(irq);
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if (WARN_ON(!irq_ops))
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err = -EINVAL;
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}
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if (err)
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goto err_out;
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per_cpu(cpu_irq, cpu) = irq;
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per_cpu(cpu_irq_ops, cpu) = irq_ops;
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return 0;
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err_out:
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|
|
@ -623,12 +743,8 @@ static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
|
|||
per_cpu(cpu_armpmu, cpu) = pmu;
|
||||
|
||||
irq = armpmu_get_cpu_irq(pmu, cpu);
|
||||
if (irq) {
|
||||
if (irq_is_percpu_devid(irq))
|
||||
enable_percpu_irq(irq, IRQ_TYPE_NONE);
|
||||
else
|
||||
enable_irq(irq);
|
||||
}
|
||||
if (irq)
|
||||
per_cpu(cpu_irq_ops, cpu)->enable_pmuirq(irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -642,12 +758,8 @@ static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
|
|||
return 0;
|
||||
|
||||
irq = armpmu_get_cpu_irq(pmu, cpu);
|
||||
if (irq) {
|
||||
if (irq_is_percpu_devid(irq))
|
||||
disable_percpu_irq(irq);
|
||||
else
|
||||
disable_irq_nosync(irq);
|
||||
}
|
||||
if (irq)
|
||||
per_cpu(cpu_irq_ops, cpu)->disable_pmuirq(irq);
|
||||
|
||||
per_cpu(cpu_armpmu, cpu) = NULL;
|
||||
|
||||
|
|
@ -868,8 +980,9 @@ int armpmu_register(struct arm_pmu *pmu)
|
|||
if (!__oprofile_cpu_pmu)
|
||||
__oprofile_cpu_pmu = pmu;
|
||||
|
||||
pr_info("enabled with %s PMU driver, %d counters available\n",
|
||||
pmu->name, pmu->num_events);
|
||||
pr_info("enabled with %s PMU driver, %d counters available%s\n",
|
||||
pmu->name, pmu->num_events,
|
||||
has_nmi ? ", using NMIs" : "");
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ struct kvm_pmu {
|
|||
bool ready;
|
||||
bool created;
|
||||
bool irq_level;
|
||||
struct irq_work overflow_work;
|
||||
};
|
||||
|
||||
#define kvm_arm_pmu_v3_ready(v) ((v)->arch.pmu.ready)
|
||||
|
|
|
|||
|
|
@ -259,6 +259,7 @@ void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu)
|
|||
|
||||
for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++)
|
||||
kvm_pmu_release_perf_event(&pmu->pmc[i]);
|
||||
irq_work_sync(&vcpu->arch.pmu.overflow_work);
|
||||
}
|
||||
|
||||
u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
|
||||
|
|
@ -435,6 +436,22 @@ void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu)
|
|||
kvm_pmu_update_state(vcpu);
|
||||
}
|
||||
|
||||
/**
|
||||
* When perf interrupt is an NMI, we cannot safely notify the vcpu corresponding
|
||||
* to the event.
|
||||
* This is why we need a callback to do it once outside of the NMI context.
|
||||
*/
|
||||
static void kvm_pmu_perf_overflow_notify_vcpu(struct irq_work *work)
|
||||
{
|
||||
struct kvm_vcpu *vcpu;
|
||||
struct kvm_pmu *pmu;
|
||||
|
||||
pmu = container_of(work, struct kvm_pmu, overflow_work);
|
||||
vcpu = kvm_pmc_to_vcpu(pmu->pmc);
|
||||
|
||||
kvm_vcpu_kick(vcpu);
|
||||
}
|
||||
|
||||
/**
|
||||
* When the perf event overflows, set the overflow status and inform the vcpu.
|
||||
*/
|
||||
|
|
@ -467,7 +484,11 @@ static void kvm_pmu_perf_overflow(struct perf_event *perf_event,
|
|||
|
||||
if (kvm_pmu_overflow_status(vcpu)) {
|
||||
kvm_make_request(KVM_REQ_IRQ_PENDING, vcpu);
|
||||
|
||||
if (!in_nmi())
|
||||
kvm_vcpu_kick(vcpu);
|
||||
else
|
||||
irq_work_queue(&vcpu->arch.pmu.overflow_work);
|
||||
}
|
||||
|
||||
cpu_pmu->pmu.start(perf_event, PERF_EF_RELOAD);
|
||||
|
|
@ -760,6 +781,9 @@ static int kvm_arm_pmu_v3_init(struct kvm_vcpu *vcpu)
|
|||
return ret;
|
||||
}
|
||||
|
||||
init_irq_work(&vcpu->arch.pmu.overflow_work,
|
||||
kvm_pmu_perf_overflow_notify_vcpu);
|
||||
|
||||
vcpu->arch.pmu.created = true;
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue