Merge branch 'pci/controller/dwc'
- Wait for link to come up only if we've initiated link training (Ajay Agarwal) - Save and restore imx6 Root Port MSI control to work around hardware defect (Richard Zhu) * pci/controller/dwc: PCI: imx6: Save and restore root port MSI control in suspend and resume PCI: dwc: Wait for link up only if link is started
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commit
99f7b80906
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@ -80,6 +80,7 @@ struct imx6_pcie {
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struct clk *pcie;
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struct clk *pcie_aux;
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struct regmap *iomuxc_gpr;
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u16 msi_ctrl;
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u32 controller_id;
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struct reset_control *pciephy_reset;
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struct reset_control *apps_reset;
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@ -1178,6 +1179,26 @@ pm_turnoff_sleep:
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usleep_range(1000, 10000);
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}
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static void imx6_pcie_msi_save_restore(struct imx6_pcie *imx6_pcie, bool save)
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{
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u8 offset;
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u16 val;
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struct dw_pcie *pci = imx6_pcie->pci;
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if (pci_msi_enabled()) {
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offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
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if (save) {
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val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
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imx6_pcie->msi_ctrl = val;
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} else {
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dw_pcie_dbi_ro_wr_en(pci);
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val = imx6_pcie->msi_ctrl;
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dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
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dw_pcie_dbi_ro_wr_dis(pci);
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}
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}
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}
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static int imx6_pcie_suspend_noirq(struct device *dev)
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{
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struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
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@ -1186,6 +1207,7 @@ static int imx6_pcie_suspend_noirq(struct device *dev)
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if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
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return 0;
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imx6_pcie_msi_save_restore(imx6_pcie, true);
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imx6_pcie_pm_turnoff(imx6_pcie);
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imx6_pcie_stop_link(imx6_pcie->pci);
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imx6_pcie_host_exit(pp);
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@ -1205,6 +1227,7 @@ static int imx6_pcie_resume_noirq(struct device *dev)
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ret = imx6_pcie_host_init(pp);
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if (ret)
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return ret;
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imx6_pcie_msi_save_restore(imx6_pcie, false);
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dw_pcie_setup_rc(pp);
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if (imx6_pcie->link_is_up)
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@ -485,14 +485,19 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
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if (ret)
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goto err_remove_edma;
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if (!dw_pcie_link_up(pci)) {
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if (dw_pcie_link_up(pci)) {
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dw_pcie_print_link_status(pci);
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} else {
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ret = dw_pcie_start_link(pci);
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if (ret)
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goto err_remove_edma;
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}
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/* Ignore errors, the link may come up later */
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dw_pcie_wait_for_link(pci);
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if (pci->ops && pci->ops->start_link) {
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ret = dw_pcie_wait_for_link(pci);
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if (ret)
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goto err_stop_link;
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}
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}
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bridge->sysdata = pp;
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@ -644,9 +644,20 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index)
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dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0);
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}
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int dw_pcie_wait_for_link(struct dw_pcie *pci)
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void dw_pcie_print_link_status(struct dw_pcie *pci)
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{
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u32 offset, val;
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offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
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dev_info(pci->dev, "PCIe Gen.%u x%u link up\n",
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FIELD_GET(PCI_EXP_LNKSTA_CLS, val),
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FIELD_GET(PCI_EXP_LNKSTA_NLW, val));
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}
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int dw_pcie_wait_for_link(struct dw_pcie *pci)
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{
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int retries;
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/* Check if the link is up or not */
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@ -662,12 +673,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci)
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return -ETIMEDOUT;
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}
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offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
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dev_info(pci->dev, "PCIe Gen.%u x%u link up\n",
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FIELD_GET(PCI_EXP_LNKSTA_CLS, val),
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FIELD_GET(PCI_EXP_LNKSTA_NLW, val));
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dw_pcie_print_link_status(pci);
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return 0;
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}
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@ -429,6 +429,7 @@ void dw_pcie_setup(struct dw_pcie *pci);
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void dw_pcie_iatu_detect(struct dw_pcie *pci);
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int dw_pcie_edma_detect(struct dw_pcie *pci);
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void dw_pcie_edma_remove(struct dw_pcie *pci);
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void dw_pcie_print_link_status(struct dw_pcie *pci);
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static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
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{
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