net/mlx5: Fix FPGA capability location
Currently, FPGA capability is located in (mdev)->caps.hca_cur,
change the location to be (mdev)->caps.fpga,
since hca_cur is reserved for HCA device capabilities.
Fixes: e29341fb3a
("net/mlx5: FPGA, Add basic support for Innova")
Signed-off-by: Inbar Karmy <inbark@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
This commit is contained in:
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38e8a5c040
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@ -71,11 +71,11 @@ int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
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return 0;
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}
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int mlx5_fpga_caps(struct mlx5_core_dev *dev, u32 *caps)
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int mlx5_fpga_caps(struct mlx5_core_dev *dev)
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{
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u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};
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return mlx5_core_access_reg(dev, in, sizeof(in), caps,
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return mlx5_core_access_reg(dev, in, sizeof(in), dev->caps.fpga,
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MLX5_ST_SZ_BYTES(fpga_cap),
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MLX5_REG_FPGA_CAP, 0, 0);
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}
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@ -65,7 +65,7 @@ struct mlx5_fpga_qp_counters {
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u64 rx_total_drop;
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};
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int mlx5_fpga_caps(struct mlx5_core_dev *dev, u32 *caps);
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int mlx5_fpga_caps(struct mlx5_core_dev *dev);
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int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query);
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int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);
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int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
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@ -139,8 +139,7 @@ int mlx5_fpga_device_start(struct mlx5_core_dev *mdev)
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if (err)
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goto out;
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err = mlx5_fpga_caps(fdev->mdev,
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fdev->mdev->caps.hca_cur[MLX5_CAP_FPGA]);
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err = mlx5_fpga_caps(fdev->mdev);
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if (err)
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goto out;
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@ -980,7 +980,6 @@ enum mlx5_cap_type {
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MLX5_CAP_RESERVED,
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MLX5_CAP_VECTOR_CALC,
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MLX5_CAP_QOS,
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MLX5_CAP_FPGA,
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/* NUM OF CAP Types */
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MLX5_CAP_NUM
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};
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@ -1110,10 +1109,10 @@ enum mlx5_mcam_feature_groups {
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MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
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#define MLX5_CAP_FPGA(mdev, cap) \
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MLX5_GET(fpga_cap, (mdev)->caps.hca_cur[MLX5_CAP_FPGA], cap)
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MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
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#define MLX5_CAP64_FPGA(mdev, cap) \
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MLX5_GET64(fpga_cap, (mdev)->caps.hca_cur[MLX5_CAP_FPGA], cap)
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MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
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enum {
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MLX5_CMD_STAT_OK = 0x0,
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@ -774,6 +774,7 @@ struct mlx5_core_dev {
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u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
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u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
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u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
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u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
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} caps;
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phys_addr_t iseg_base;
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struct mlx5_init_seg __iomem *iseg;
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