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drm/amd/display: Check for flip pending before locking pipes. 

[Why]
When running a game/benchmark with v-sync disabled, disabling a plane
(which is v-sync) can cause an underflow. This is due to flips that are
pending before pipe locking being applied after locks are released and
pipes have been re-arranged or disconnected. This can potentially apply
a flip on the incorrect pipe.

[How]
Check that any pending flips are cleared before locking any pipes to
ensure flips are applied on the correct pipes.

Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Taimur Hassan 2020-09-10 10:13:42 -04:00 committed by Alex Deucher
parent a9edc81564
commit 99d1437aa0
4 changed files with 14 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -2324,7 +2324,6 @@ static void commit_planes_for_stream(struct dc *dc,
enum surface_update_type update_type,
struct dc_state *context)
{
bool mpcc_disconnected = false;
int i, j;
struct pipe_ctx *top_pipe_to_program = NULL;
@ -2355,14 +2354,8 @@ static void commit_planes_for_stream(struct dc *dc,
context_clock_trace(dc, context);
}
if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock &&
dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
dc->hwss.interdependent_update_lock(dc, context, true);
mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
dc->hwss.interdependent_update_lock(dc, context, false);
if (mpcc_disconnected)
dc->hwss.wait_for_pending_cleared(dc, context);
}
if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock && dc->hwss.wait_for_pending_cleared)
dc->hwss.disconnect_pipes(dc, context);
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

12
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -2761,7 +2761,7 @@ static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
return NULL;
}
bool dcn10_disconnect_pipes(
void dcn10_disconnect_pipes(
struct dc *dc,
struct dc_state *context)
{
@ -2772,6 +2772,10 @@ bool dcn10_disconnect_pipes(
bool mpcc_disconnected = false;
struct pipe_ctx *old_pipe;
struct pipe_ctx *new_pipe;
dc->hwss.wait_for_pending_cleared(dc, context);
dc->hwss.interdependent_update_lock(dc, context, true);
DC_LOGGER_INIT(dc->ctx->logger);
/* Set pipe update flags and lock pipes */
@ -2874,7 +2878,11 @@ bool dcn10_disconnect_pipes(
}
}
}
return mpcc_disconnected;
dc->hwss.interdependent_update_lock(dc, context, false);
if (mpcc_disconnected)
dc->hwss.wait_for_pending_cleared(dc, context);
}
void dcn10_wait_for_pending_cleared(struct dc *dc,

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
View File

@ -194,7 +194,7 @@ void dcn10_get_surface_visual_confirm_color(
void dcn10_get_hdr_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color);
bool dcn10_disconnect_pipes(
void dcn10_disconnect_pipes(
struct dc *dc,
struct dc_state *context);

2
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
View File

@ -67,7 +67,7 @@ struct hw_sequencer_funcs {
int num_planes, struct dc_state *context);
void (*program_front_end_for_ctx)(struct dc *dc,
struct dc_state *context);
bool (*disconnect_pipes)(struct dc *dc,
void (*disconnect_pipes)(struct dc *dc,
struct dc_state *context);
void (*wait_for_pending_cleared)(struct dc *dc,
struct dc_state *context);