stmmac: dwmac-mediatek: add support for mt2712
Add Ethernet support for MediaTek SoCs from the mt2712 family Signed-off-by: Biao Huang <biao.huang@mediatek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Biao Huang
David S. Miller
parent
3f9b7eeea0
commit
9992f37e34
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@ -75,6 +75,14 @@ config DWMAC_LPC18XX
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---help---
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Support for NXP LPC18xx/43xx DWMAC Ethernet.
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config DWMAC_MEDIATEK
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tristate "MediaTek MT27xx GMAC support"
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depends on OF && (ARCH_MEDIATEK || COMPILE_TEST)
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help
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Support for MediaTek GMAC Ethernet controller.
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This selects the MT2712 SoC support for the stmmac driver.
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config DWMAC_MESON
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tristate "Amlogic Meson dwmac support"
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default ARCH_MESON
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@ -13,6 +13,7 @@ obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o
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obj-$(CONFIG_DWMAC_ANARION) += dwmac-anarion.o
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obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o
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obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o
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obj-$(CONFIG_DWMAC_MEDIATEK) += dwmac-mediatek.o
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obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o
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obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas.o
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obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o
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@ -0,0 +1,408 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_net.h>
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#include <linux/regmap.h>
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#include <linux/stmmac.h>
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#include "stmmac.h"
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#include "stmmac_platform.h"
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/* Peri Configuration register for mt2712 */
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#define PERI_ETH_PHY_INTF_SEL 0x418
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#define PHY_INTF_MII 0
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#define PHY_INTF_RGMII 1
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#define PHY_INTF_RMII 4
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#define RMII_CLK_SRC_RXC BIT(4)
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#define RMII_CLK_SRC_INTERNAL BIT(5)
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#define PERI_ETH_DLY 0x428
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#define ETH_DLY_GTXC_INV BIT(6)
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#define ETH_DLY_GTXC_ENABLE BIT(5)
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#define ETH_DLY_GTXC_STAGES GENMASK(4, 0)
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#define ETH_DLY_TXC_INV BIT(20)
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#define ETH_DLY_TXC_ENABLE BIT(19)
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#define ETH_DLY_TXC_STAGES GENMASK(18, 14)
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#define ETH_DLY_RXC_INV BIT(13)
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#define ETH_DLY_RXC_ENABLE BIT(12)
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#define ETH_DLY_RXC_STAGES GENMASK(11, 7)
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#define PERI_ETH_DLY_FINE 0x800
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#define ETH_RMII_DLY_TX_INV BIT(2)
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#define ETH_FINE_DLY_GTXC BIT(1)
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#define ETH_FINE_DLY_RXC BIT(0)
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struct mac_delay_struct {
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u32 tx_delay;
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u32 rx_delay;
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bool tx_inv;
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bool rx_inv;
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bool fine_tune;
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};
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struct mediatek_dwmac_plat_data {
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const struct mediatek_dwmac_variant *variant;
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struct mac_delay_struct mac_delay;
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struct clk_bulk_data *clks;
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struct device_node *np;
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struct regmap *peri_regmap;
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struct device *dev;
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int phy_mode;
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bool rmii_rxc;
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};
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struct mediatek_dwmac_variant {
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int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);
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int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);
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/* clock ids to be requested */
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const char * const *clk_list;
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int num_clks;
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u32 dma_bit_mask;
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u32 rx_delay_max;
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u32 tx_delay_max;
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};
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/* list of clocks required for mac */
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static const char * const mt2712_dwmac_clk_l[] = {
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"axi", "apb", "mac_main", "ptp_ref"
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};
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static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
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{
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int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0;
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u32 intf_val = 0;
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/* select phy interface in top control domain */
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switch (plat->phy_mode) {
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case PHY_INTERFACE_MODE_MII:
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intf_val |= PHY_INTF_MII;
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break;
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case PHY_INTERFACE_MODE_RMII:
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intf_val |= (PHY_INTF_RMII | rmii_rxc);
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_ID:
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intf_val |= PHY_INTF_RGMII;
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break;
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default:
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dev_err(plat->dev, "phy interface not supported\n");
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return -EINVAL;
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}
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regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val);
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return 0;
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}
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static void mt2712_delay_ps2stage(struct mac_delay_struct *mac_delay)
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{
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if (mac_delay->fine_tune) {
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/* 170ps per stage for fine tune delay macro circuit*/
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mac_delay->tx_delay /= 170;
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mac_delay->rx_delay /= 170;
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} else {
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/* 550ps per stage for coarse tune delay macro circuit*/
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mac_delay->tx_delay /= 550;
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mac_delay->rx_delay /= 550;
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}
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}
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static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
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{
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struct mac_delay_struct *mac_delay = &plat->mac_delay;
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u32 delay_val = 0, fine_val = 0;
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mt2712_delay_ps2stage(mac_delay);
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switch (plat->phy_mode) {
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case PHY_INTERFACE_MODE_MII:
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delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* the rmii reference clock is from external phy,
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* and the property "rmii_rxc" indicates which pin(TXC/RXC)
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* the reference clk is connected to. The reference clock is a
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* received signal, so rx_delay/rx_inv are used to indicate
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* the reference clock timing adjustment
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*/
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if (plat->rmii_rxc) {
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/* the rmii reference clock from outside is connected
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* to RXC pin, the reference clock will be adjusted
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* by RXC delay macro circuit.
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*/
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delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
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} else {
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/* the rmii reference clock from outside is connected
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* to TXC pin, the reference clock will be adjusted
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* by TXC delay macro circuit.
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*/
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delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);
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}
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/* tx_inv will inverse the tx clock inside mac relateive to
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* reference clock from external phy,
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* and this bit is located in the same register with fine-tune
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*/
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if (mac_delay->tx_inv)
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fine_val = ETH_RMII_DLY_TX_INV;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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/* the PHY is not responsible for inserting any internal
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* delay by itself in PHY_INTERFACE_MODE_RGMII case,
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* so Ethernet MAC will insert delays for both transmit
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* and receive path here.
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*/
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if (mac_delay->fine_tune)
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fine_val = ETH_FINE_DLY_GTXC | ETH_FINE_DLY_RXC;
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delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
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break;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* the PHY should insert an internal delay for the transmit
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* path in PHY_INTERFACE_MODE_RGMII_TXID case,
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* so Ethernet MAC will insert the delay for receive path here.
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*/
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if (mac_delay->fine_tune)
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fine_val = ETH_FINE_DLY_RXC;
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delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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/* the PHY should insert an internal delay for the receive
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* path in PHY_INTERFACE_MODE_RGMII_RXID case,
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* so Ethernet MAC will insert the delay for transmit path here.
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*/
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if (mac_delay->fine_tune)
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fine_val = ETH_FINE_DLY_GTXC;
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delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv);
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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/* the PHY should insert internal delays for both transmit
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* and receive path in PHY_INTERFACE_MODE_RGMII_RXID case,
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* so Ethernet MAC will NOT insert any delay here.
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*/
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break;
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default:
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dev_err(plat->dev, "phy interface not supported\n");
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return -EINVAL;
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}
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regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val);
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regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val);
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return 0;
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}
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static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
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.dwmac_set_phy_interface = mt2712_set_interface,
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.dwmac_set_delay = mt2712_set_delay,
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.clk_list = mt2712_dwmac_clk_l,
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.num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l),
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.dma_bit_mask = 33,
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.rx_delay_max = 17600,
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.tx_delay_max = 17600,
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};
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static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
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{
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struct mac_delay_struct *mac_delay = &plat->mac_delay;
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u32 tx_delay_ps, rx_delay_ps;
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plat->peri_regmap = syscon_regmap_lookup_by_phandle(plat->np, "mediatek,pericfg");
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if (IS_ERR(plat->peri_regmap)) {
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dev_err(plat->dev, "Failed to get pericfg syscon\n");
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return PTR_ERR(plat->peri_regmap);
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}
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plat->phy_mode = of_get_phy_mode(plat->np);
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if (plat->phy_mode < 0) {
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dev_err(plat->dev, "not find phy-mode\n");
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return -EINVAL;
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}
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if (!of_property_read_u32(plat->np, "mediatek,tx-delay-ps", &tx_delay_ps)) {
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if (tx_delay_ps < plat->variant->tx_delay_max) {
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mac_delay->tx_delay = tx_delay_ps;
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} else {
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dev_err(plat->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps);
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return -EINVAL;
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}
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}
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if (!of_property_read_u32(plat->np, "mediatek,rx-delay-ps", &rx_delay_ps)) {
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if (rx_delay_ps < plat->variant->rx_delay_max) {
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mac_delay->rx_delay = rx_delay_ps;
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} else {
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dev_err(plat->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps);
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return -EINVAL;
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}
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}
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mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse");
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mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse");
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mac_delay->fine_tune = of_property_read_bool(plat->np, "mediatek,fine-tune");
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plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc");
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return 0;
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}
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static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat)
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{
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const struct mediatek_dwmac_variant *variant = plat->variant;
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int i, num = variant->num_clks;
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plat->clks = devm_kcalloc(plat->dev, num, sizeof(*plat->clks), GFP_KERNEL);
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if (!plat->clks)
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return -ENOMEM;
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for (i = 0; i < num; i++)
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plat->clks[i].id = variant->clk_list[i];
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return devm_clk_bulk_get(plat->dev, num, plat->clks);
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}
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static int mediatek_dwmac_init(struct platform_device *pdev, void *priv)
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{
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struct mediatek_dwmac_plat_data *plat = priv;
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const struct mediatek_dwmac_variant *variant = plat->variant;
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int ret;
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ret = dma_set_mask_and_coherent(plat->dev, DMA_BIT_MASK(variant->dma_bit_mask));
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if (ret) {
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dev_err(plat->dev, "No suitable DMA available, err = %d\n", ret);
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return ret;
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}
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ret = variant->dwmac_set_phy_interface(plat);
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if (ret) {
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dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret);
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return ret;
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}
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ret = variant->dwmac_set_delay(plat);
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if (ret) {
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dev_err(plat->dev, "failed to set delay value, err = %d\n", ret);
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return ret;
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}
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ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks);
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if (ret) {
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dev_err(plat->dev, "failed to enable clks, err = %d\n", ret);
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return ret;
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}
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return 0;
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}
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static void mediatek_dwmac_exit(struct platform_device *pdev, void *priv)
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{
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struct mediatek_dwmac_plat_data *plat = priv;
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const struct mediatek_dwmac_variant *variant = plat->variant;
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clk_bulk_disable_unprepare(variant->num_clks, plat->clks);
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}
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static int mediatek_dwmac_probe(struct platform_device *pdev)
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{
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struct mediatek_dwmac_plat_data *priv_plat;
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struct plat_stmmacenet_data *plat_dat;
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struct stmmac_resources stmmac_res;
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int ret;
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priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat), GFP_KERNEL);
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if (!priv_plat)
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return -ENOMEM;
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priv_plat->variant = of_device_get_match_data(&pdev->dev);
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if (!priv_plat->variant) {
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dev_err(&pdev->dev, "Missing dwmac-mediatek variant\n");
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return -EINVAL;
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}
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priv_plat->dev = &pdev->dev;
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priv_plat->np = pdev->dev.of_node;
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ret = mediatek_dwmac_config_dt(priv_plat);
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if (ret)
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return ret;
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ret = mediatek_dwmac_clk_init(priv_plat);
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if (ret)
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return ret;
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ret = stmmac_get_platform_resources(pdev, &stmmac_res);
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if (ret)
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return ret;
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plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
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if (IS_ERR(plat_dat))
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return PTR_ERR(plat_dat);
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plat_dat->interface = priv_plat->phy_mode;
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/* clk_csr_i = 250-300MHz & MDC = clk_csr_i/124 */
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plat_dat->clk_csr = 5;
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plat_dat->has_gmac4 = 1;
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plat_dat->has_gmac = 0;
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plat_dat->pmt = 0;
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plat_dat->maxmtu = ETH_DATA_LEN;
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plat_dat->bsp_priv = priv_plat;
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plat_dat->init = mediatek_dwmac_init;
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||||
plat_dat->exit = mediatek_dwmac_exit;
|
||||
mediatek_dwmac_init(pdev, priv_plat);
|
||||
|
||||
ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
|
||||
if (ret) {
|
||||
stmmac_remove_config_dt(pdev, plat_dat);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mediatek_dwmac_match[] = {
|
||||
{ .compatible = "mediatek,mt2712-gmac",
|
||||
.data = &mt2712_gmac_variant },
|
||||
{ }
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, mediatek_dwmac_match);
|
||||
|
||||
static struct platform_driver mediatek_dwmac_driver = {
|
||||
.probe = mediatek_dwmac_probe,
|
||||
.remove = stmmac_pltfr_remove,
|
||||
.driver = {
|
||||
.name = "dwmac-mediatek",
|
||||
.pm = &stmmac_pltfr_pm_ops,
|
||||
.of_match_table = mediatek_dwmac_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(mediatek_dwmac_driver);
|
||||
Loading…
Reference in New Issue