drm/amd/display: Stereo 3D support in VSC
[Why] Need to add strere 3D information in VSC [How] Update mod_build_vsc_infopacket with stereo info Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -48,9 +48,12 @@ static void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
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unsigned int i;
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unsigned int pixelEncoding = 0;
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unsigned int colorimetryFormat = 0;
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bool stereo3dSupport = false;
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if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE)
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if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE) {
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vscPacketRevision = 1;
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stereo3dSupport = true;
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}
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/*VSC packet set to 2 when DP revision >= 1.2*/
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if (stream->psr_version != 0)
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@ -94,12 +97,59 @@ static void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
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info_packet->hb2 = 0x01; // 01h = Revision number. VSC SDP supporting 3D stereo only
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info_packet->hb3 = 0x01; // 01h = VSC SDP supporting 3D stereo only (HB2 = 01h).
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if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_INBAND_FA)
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info_packet->sb[0] = 0x1;
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info_packet->valid = true;
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}
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if (stereo3dSupport) {
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/* ==============================================================================================================|
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* A. STEREO 3D
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* ==============================================================================================================|
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* VSC Payload (1 byte) From DP1.2 spec
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*
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* Bits 3:0 (Stereo Interface Method Code) | Bits 7:4 (Stereo Interface Method Specific Parameter)
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* -----------------------------------------------------------------------------------------------------
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* 0 = Non Stereo Video | Must be set to 0x0
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* -----------------------------------------------------------------------------------------------------
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* 1 = Frame/Field Sequential | 0x0: L + R view indication based on MISC1 bit 2:1
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* | 0x1: Right when Stereo Signal = 1
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* | 0x2: Left when Stereo Signal = 1
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* | (others reserved)
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* -----------------------------------------------------------------------------------------------------
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* 2 = Stacked Frame | 0x0: Left view is on top and right view on bottom
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* | (others reserved)
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* -----------------------------------------------------------------------------------------------------
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* 3 = Pixel Interleaved | 0x0: horiz interleaved, right view pixels on even lines
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* | 0x1: horiz interleaved, right view pixels on odd lines
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* | 0x2: checker board, start with left view pixel
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* | 0x3: vertical interleaved, start with left view pixels
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* | 0x4: vertical interleaved, start with right view pixels
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* | (others reserved)
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* -----------------------------------------------------------------------------------------------------
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* 4 = Side-by-side | 0x0: left half represents left eye view
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* | 0x1: left half represents right eye view
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*/
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switch (stream->timing.timing_3d_format) {
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case TIMING_3D_FORMAT_HW_FRAME_PACKING:
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case TIMING_3D_FORMAT_SW_FRAME_PACKING:
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case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
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case TIMING_3D_FORMAT_TB_SW_PACKED:
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info_packet->sb[0] = 0x02; // Stacked Frame, Left view is on top and right view on bottom.
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break;
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case TIMING_3D_FORMAT_DP_HDMI_INBAND_FA:
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case TIMING_3D_FORMAT_INBAND_FA:
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info_packet->sb[0] = 0x01; // Frame/Field Sequential, L + R view indication based on MISC1 bit 2:1
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break;
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case TIMING_3D_FORMAT_SIDE_BY_SIDE:
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case TIMING_3D_FORMAT_SBS_SW_PACKED:
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info_packet->sb[0] = 0x04; // Side-by-side
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break;
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default:
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info_packet->sb[0] = 0x00; // No Stereo Video, Shall be cleared to 0x0.
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break;
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}
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}
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/* 05h = VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/Colorimetry Format indication.
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* Added in DP1.3, a DP Source device is allowed to indicate the pixel encoding/colorimetry
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* format to the DP Sink device with VSC SDP only when the DP Sink device supports it
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