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net/mlx5: DR, Skip source port matching on FDB RX domain 

The FDB RX pipe is connected to the wire and the source port for all
incoming packets equals to wire, single uplink port per PF, this means
there is no point of matching on the source port in such case.
Once we recognize such case, we will optimize the RX steering rule.
Note that in such case we clean both source_eswitch_owner_vhca_id and
source_port.

Signed-off-by: Alex Vesker <valex@mellanox.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Yevgeny Kliteynik 2021-07-04 17:48:24 +03:00 committed by Saeed Mahameed
parent 63b85f49c0
commit 990467f8af
1 changed files with 13 additions and 1 deletions
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14
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c
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@ -396,6 +396,7 @@ static int dr_matcher_set_ste_builders(struct mlx5dr_matcher *matcher,
struct mlx5dr_domain *dmn = matcher->tbl->dmn;
struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx;
struct mlx5dr_match_param mask = {};
bool allow_empty_match = false;
struct mlx5dr_ste_build *sb;
bool inner, rx;
int idx = 0;
@ -428,6 +429,16 @@ static int dr_matcher_set_ste_builders(struct mlx5dr_matcher *matcher,
if (ret)
return ret;
/* Optimize RX pipe by reducing source port match, since
* the FDB RX part is connected only to the wire.
*/
if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB &&
rx && mask.misc.source_port) {
mask.misc.source_port = 0;
mask.misc.source_eswitch_owner_vhca_id = 0;
allow_empty_match = true;
}
/* Outer */
if (matcher->match_criteria & (DR_MATCHER_CRITERIA_OUTER |
DR_MATCHER_CRITERIA_MISC |
@ -619,7 +630,8 @@ static int dr_matcher_set_ste_builders(struct mlx5dr_matcher *matcher,
}
/* Empty matcher, takes all */
if (matcher->match_criteria == DR_MATCHER_CRITERIA_EMPTY)
if ((!idx && allow_empty_match) ||
matcher->match_criteria == DR_MATCHER_CRITERIA_EMPTY)
mlx5dr_ste_build_empty_always_hit(&sb[idx++], rx);
if (idx == 0) {