cxgb4 : Update fw interface file for DCBx support. Adds all the required fields to fw interface to communicate DCBx info
Signed-off-by: Anish Bhatt <anish@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Anish Bhatt
David S. Miller
parent
9f8b93cb32
commit
989594e2f2
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@ -46,9 +46,11 @@ enum fw_retval {
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FW_EFAULT = 14, /* bad address; fw bad */
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FW_EBUSY = 16, /* resource busy */
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FW_EEXIST = 17, /* file exists */
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FW_ENODEV = 19, /* no such device */
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FW_EINVAL = 22, /* invalid argument */
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FW_ENOSPC = 28, /* no space left on device */
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FW_ENOSYS = 38, /* functionality not implemented */
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FW_ENODATA = 61, /* no data available */
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FW_EPROTO = 71, /* protocol error */
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FW_EADDRINUSE = 98, /* address already in use */
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FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
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@ -989,6 +991,7 @@ enum fw_params_param_dmaq {
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FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
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FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
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FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
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FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
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};
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#define FW_PARAMS_MNEM(x) ((x) << 24)
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@ -1422,6 +1425,7 @@ struct fw_vi_enable_cmd {
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#define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0)
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#define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31)
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#define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30)
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#define FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << 28)
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#define FW_VI_ENABLE_CMD_LED (1U << 29)
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/* VI VF stats offset definitions */
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@ -1594,6 +1598,9 @@ enum fw_port_action {
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FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
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FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
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FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
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FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
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FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
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FW_PORT_ACTION_DCB_READ_DET = 0x0008,
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FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
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FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
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FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
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@ -1637,6 +1644,14 @@ enum fw_port_dcb_type {
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FW_PORT_DCB_TYPE_PRIORATE = 0x02,
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FW_PORT_DCB_TYPE_PFC = 0x03,
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FW_PORT_DCB_TYPE_APP_ID = 0x04,
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FW_PORT_DCB_TYPE_CONTROL = 0x05,
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};
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enum fw_port_dcb_feature_state {
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FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
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FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
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FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
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FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
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};
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struct fw_port_cmd {
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@ -1648,9 +1663,11 @@ struct fw_port_cmd {
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__be32 r;
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} l1cfg;
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struct fw_port_l2cfg {
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__be16 ctlbf_to_ivlan0;
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__u8 ctlbf;
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__u8 ovlan3_to_ivlan0;
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__be16 ivlantype;
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__be32 txipg_pkd;
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__be16 txipg_force_pinfo;
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__be16 mtu;
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__be16 ovlan0mask;
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__be16 ovlan0type;
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__be16 ovlan1mask;
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@ -1666,24 +1683,60 @@ struct fw_port_cmd {
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__be16 acap;
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__be16 mtu;
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__u8 cbllen;
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__u8 r9;
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__be32 r10;
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__be64 r11;
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__u8 auxlinfo;
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__u8 dcbxdis_pkd;
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__u8 r8_lo[3];
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__be64 r9;
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} info;
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struct fw_port_ppp {
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__be32 pppen_to_ncsich;
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__be32 r11;
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} ppp;
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struct fw_port_dcb {
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__be16 cfg;
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u8 up_map;
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u8 sf_cfgrc;
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__be16 prot_ix;
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u8 pe7_to_pe0;
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u8 numTCPFCs;
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__be32 pgid0_to_pgid7;
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__be32 numTCs_oui;
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u8 pgpc[8];
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struct fw_port_diags {
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__u8 diagop;
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__u8 r[3];
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__be32 diagval;
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} diags;
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union fw_port_dcb {
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struct fw_port_dcb_pgid {
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__u8 type;
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__u8 apply_pkd;
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__u8 r10_lo[2];
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__be32 pgid;
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__be64 r11;
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} pgid;
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struct fw_port_dcb_pgrate {
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__u8 type;
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__u8 apply_pkd;
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__u8 r10_lo[5];
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__u8 num_tcs_supported;
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__u8 pgrate[8];
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} pgrate;
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struct fw_port_dcb_priorate {
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__u8 type;
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__u8 apply_pkd;
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__u8 r10_lo[6];
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__u8 strict_priorate[8];
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} priorate;
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struct fw_port_dcb_pfc {
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__u8 type;
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__u8 pfcen;
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__u8 r10[5];
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__u8 max_pfc_tcs;
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__be64 r11;
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} pfc;
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struct fw_port_app_priority {
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__u8 type;
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__u8 r10[2];
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__u8 idx;
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__u8 user_prio_map;
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__u8 sel_field;
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__be16 protocolid;
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__be64 r12;
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} app_priority;
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struct fw_port_dcb_control {
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__u8 type;
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__u8 all_syncd_pkd;
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__be16 pfc_state_to_app_state;
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__be32 r11;
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__be64 r12;
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} control;
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} dcb;
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} u;
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};
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@ -1720,6 +1773,10 @@ struct fw_port_cmd {
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#define FW_PORT_CMD_MODTYPE_MASK 0x1f
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#define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK)
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#define FW_PORT_CMD_DCBXDIS (1U << 7)
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#define FW_PORT_CMD_APPLY (1U << 7)
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#define FW_PORT_CMD_ALL_SYNCD (1U << 7)
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#define FW_PORT_CMD_PPPEN(x) ((x) << 31)
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#define FW_PORT_CMD_TPSRC(x) ((x) << 28)
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#define FW_PORT_CMD_NCSISRC(x) ((x) << 24)
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