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Add initial genpd support for omaps to drop more platform data 

We now drop legacy platform data for RTC on am3, am4 and dra7.
 And we add initial genpd support for PRM (Power and Reset Manager)
 and use it to drop legacy platform data for am3 sgx and omap4/5
 l4_abe interconnect instance.
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Merge tag 'omap-for-v5.10/ti-sysc-drop-pdata-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc

Add initial genpd support for omaps to drop more platform data

We now drop legacy platform data for RTC on am3, am4 and dra7.
And we add initial genpd support for PRM (Power and Reset Manager)
and use it to drop legacy platform data for am3 sgx and omap4/5
l4_abe interconnect instance.

* tag 'omap-for-v5.10/ti-sysc-drop-pdata-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Drop legacy platform data for dra7 rtcss
  ARM: OMAP2+: Drop legacy platform data for am3 and am4 rtc
  soc: ti: pm33xx: Simplify RTC usage to prepare to drop platform data
  ARM: dts: Configure omap4 and 5 l4_abe for genpd and drop platform data
  ARM: dts: Configure am3 and am4 sgx for genpd and drop platform data
  soc: ti: omap-prm: Configure omap4 and 5 l4_abe power domain
  soc: ti: omap-prm: Configure sgx power domain for am3 and am4
  soc: ti: omap-prm: Add basic power domain support
  dt-bindings: omap: Update PRM binding for genpd

Link: https://lore.kernel.org/r/pull-1599132307-761202@atomide.com-2
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2020-09-13 11:17:41 -07:00
parent 63e850f1cd 0d7ce5c5c4
commit 989286ffe8
24 changed files with 345 additions and 268 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/omap/prm-inst.txt
View File

@ -18,6 +18,7 @@ Required properties:
(base address and length)
Optional properties:
- #power-domain-cells: Should be 0 if the instance is a power domain provider.
- #reset-cells: Should be 1 if the PRM instance in question supports resets.
Example:
@ -25,5 +26,6 @@ Example:
prm_dsp2: prm@1b00 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1b00 0x40>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};

1
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@ -425,7 +425,6 @@
target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "rtc";
reg = <0x3e074 0x4>,
<0x3e078 0x4>;
reg-names = "rev", "sysc";

2
arch/arm/boot/dts/am33xx.dtsi
View File

@ -578,6 +578,7 @@
<SYSC_IDLE_SMART>;
clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
clock-names = "fck";
power-domains = <&prm_gfx>;
resets = <&prm_gfx 0>;
reset-names = "rstctrl";
#address-cells = <1>;
@ -617,6 +618,7 @@
prm_gfx: prm@1100 {
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
reg = <0x1100 0x100>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
};

2
arch/arm/boot/dts/am4372.dtsi
View File

@ -517,6 +517,7 @@
<SYSC_IDLE_SMART>;
clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
clock-names = "fck";
power-domains = <&prm_gfx>;
resets = <&prm_gfx 0>;
reset-names = "rstctrl";
#address-cells = <1>;
@ -533,6 +534,7 @@
prm_gfx: prm@400 {
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
reg = <0x400 0x100>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};

3
arch/arm/boot/dts/am437x-l4.dtsi
View File

@ -409,9 +409,8 @@
ranges = <0x0 0x39000 0x1000>;
};
target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */
rtc_target: target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "rtc";
reg = <0x3e074 0x4>,
<0x3e078 0x4>;
reg-names = "rev", "sysc";

4
arch/arm/boot/dts/am43x-epos-evm.dts
View File

@ -833,6 +833,10 @@
status = "okay";
};
&rtc_target {
status = "disabled";
};
&tscadc {
status = "okay";

1
arch/arm/boot/dts/dra7-l4.dtsi
View File

@ -3561,7 +3561,6 @@
rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "rtcss";
reg = <0x38074 0x4>,
<0x38078 0x4>;
reg-names = "rev", "sysc";

6
arch/arm/boot/dts/omap4-l4-abe.dtsi
View File

@ -1,14 +1,16 @@
&l4_abe { /* 0x40100000 */
compatible = "ti,omap4-l4-abe", "simple-bus";
compatible = "ti,omap4-l4-abe", "simple-pm-bus";
reg = <0x40100000 0x400>,
<0x40100400 0x400>;
reg-names = "la", "ap";
power-domains = <&prm_abe>;
/* OMAP4_L4_ABE_CLKCTRL is read-only */
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
<0x49000000 0x49000000 0x100000>;
segment@0 { /* 0x40100000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges =

6
arch/arm/boot/dts/omap4.dtsi
View File

@ -658,6 +658,12 @@
#reset-cells = <1>;
};
prm_abe: prm@500 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x500 0x100>;
#power-domain-cells = <0>;
};
prm_core: prm@700 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x700 0x100>;

6
arch/arm/boot/dts/omap5-l4-abe.dtsi
View File

@ -1,14 +1,16 @@
&l4_abe { /* 0x40100000 */
compatible = "ti,omap5-l4-abe", "simple-bus";
compatible = "ti,omap5-l4-abe", "simple-pm-bus";
reg = <0x40100000 0x400>,
<0x40100400 0x400>;
reg-names = "la", "ap";
power-domains = <&prm_abe>;
/* OMAP5_L4_ABE_CLKCTRL is read-only */
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
<0x49000000 0x49000000 0x100000>;
segment@0 { /* 0x40100000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges =

6
arch/arm/boot/dts/omap5.dtsi
View File

@ -674,6 +674,12 @@
#reset-cells = <1>;
};
prm_abe: prm@500 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x500 0x100>;
#power-domain-cells = <0>;
};
prm_core: prm@700 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x700 0x100>;

1
arch/arm/mach-omap2/Kconfig
View File

@ -7,6 +7,7 @@ config ARCH_OMAP2
depends on ARCH_MULTI_V6
select ARCH_OMAP2PLUS
select CPU_V6
select PM_GENERIC_DOMAINS if PM
select SOC_HAS_OMAP2_SDRC
config ARCH_OMAP3

2
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
View File

@ -26,7 +26,6 @@ extern struct omap_hwmod_ocp_if am33xx_mpu__prcm;
extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main;
extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main;
extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc;
extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2;
extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc;
@ -43,7 +42,6 @@ extern struct omap_hwmod am33xx_ocmcram_hwmod;
extern struct omap_hwmod am33xx_smartreflex0_hwmod;
extern struct omap_hwmod am33xx_smartreflex1_hwmod;
extern struct omap_hwmod am33xx_gpmc_hwmod;
extern struct omap_hwmod am33xx_rtc_hwmod;
extern struct omap_hwmod_class am33xx_emif_hwmod_class;
extern struct omap_hwmod_class am33xx_l4_hwmod_class;

24
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
View File

@ -74,30 +74,6 @@ struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* gfx -> l3 main */
struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
.master = &am33xx_gfx_hwmod,
.slave = &am33xx_l3_main_hwmod,
.clk = "dpll_core_m4_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3 main -> gfx */
struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_gfx_hwmod,
.clk = "dpll_core_m4_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 wkup -> rtc */
struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_rtc_hwmod,
.clk = "clkdiv32k_ick",
.user = OCP_USER_MPU,
};
/* l3s cfg -> gpmc */
struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
.master = &am33xx_l3_s_hwmod,

77
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
View File

@ -26,7 +26,6 @@
#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
#define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
/*
* 'l3' class
@ -133,30 +132,6 @@ struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
.name = "wkup_m3",
};
/* gfx */
/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
.name = "gfx",
};
static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
{ .name = "gfx", .rst_shift = 0, .st_shift = 0},
};
struct omap_hwmod am33xx_gfx_hwmod = {
.name = "gfx",
.class = &am33xx_gfx_hwmod_class,
.clkdm_name = "gfx_l3_clkdm",
.main_clk = "gfx_fck_div_ck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
.rst_lines = am33xx_gfx_resets,
.rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
};
/*
* 'prcm' class
* power and reset manager (whole prcm infrastructure)
@ -274,67 +249,24 @@ struct omap_hwmod am33xx_gpmc_hwmod = {
},
};
/*
* 'rtc' class
* rtc subsystem
*/
static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
.rev_offs = 0x0074,
.sysc_offs = 0x0078,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO |
SIDLE_SMART | SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type3,
};
static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
.name = "rtc",
.sysc = &am33xx_rtc_sysc,
.unlock = &omap_hwmod_rtc_unlock,
.lock = &omap_hwmod_rtc_lock,
};
struct omap_hwmod am33xx_rtc_hwmod = {
.name = "rtc",
.class = &am33xx_rtc_hwmod_class,
.clkdm_name = "l4_rtc_clkdm",
.main_clk = "clk_32768_ck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static void omap_hwmod_am33xx_clkctrl(void)
{
CLKCTRL(am33xx_smartreflex0_hwmod,
AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex1_hwmod,
AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
}
static void omap_hwmod_am33xx_rst(void)
{
RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
}
void omap_hwmod_am33xx_reg(void)
{
omap_hwmod_am33xx_clkctrl();
omap_hwmod_am33xx_rst();
}
static void omap_hwmod_am43xx_clkctrl(void)
@ -343,25 +275,16 @@ static void omap_hwmod_am43xx_clkctrl(void)
AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex1_hwmod,
AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
}
static void omap_hwmod_am43xx_rst(void)
{
RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
}
void omap_hwmod_am43xx_reg(void)
{
omap_hwmod_am43xx_clkctrl();
omap_hwmod_am43xx_rst();
}

3
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View File

@ -274,16 +274,13 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__l4_hs,
&am33xx_l3_main__l3_s,
&am33xx_l3_main__l3_instr,
&am33xx_l3_main__gfx,
&am33xx_l3_s__l3_main,
&am33xx_wkup_m3__l4_wkup,
&am33xx_gfx__l3_main,
&am33xx_l3_main__debugss,
&am33xx_l4_wkup__wkup_m3,
&am33xx_l4_wkup__control,
&am33xx_l4_wkup__smartreflex0,
&am33xx_l4_wkup__smartreflex1,
&am33xx_l4_wkup__rtc,
&am33xx_l3_s__gpmc,
&am33xx_l3_main__ocmc,
NULL,

10
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
View File

@ -143,11 +143,9 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am43xx_l3_main__l4_hs,
&am33xx_l3_main__l3_s,
&am33xx_l3_main__l3_instr,
&am33xx_l3_main__gfx,
&am33xx_l3_s__l3_main,
&am43xx_l3_main__emif,
&am43xx_wkup_m3__l4_wkup,
&am33xx_gfx__l3_main,
&am43xx_l4_wkup__wkup_m3,
&am43xx_l4_wkup__control,
&am43xx_l4_wkup__smartreflex0,
@ -157,11 +155,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
NULL,
};
static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_wkup__rtc,
NULL,
};
int __init am43xx_hwmod_init(void)
{
int ret;
@ -170,8 +163,5 @@ int __init am43xx_hwmod_init(void)
omap_hwmod_init();
ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
if (!ret && of_machine_is_compatible("ti,am4372"))
ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);
return ret;
}

33
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View File

@ -124,21 +124,6 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
.name = "l4",
};
/* l4_abe */
static struct omap_hwmod omap44xx_l4_abe_hwmod = {
.name = "l4_abe",
.class = &omap44xx_l4_hwmod_class,
.clkdm_name = "abe_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
.lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
},
},
};
/* l4_cfg */
static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
.name = "l4_cfg",
@ -771,22 +756,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
.master = &omap44xx_l3_main_1_hwmod,
.slave = &omap44xx_l4_abe_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* mpu -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
.master = &omap44xx_mpu_hwmod,
.slave = &omap44xx_l4_abe_hwmod,
.clk = "ocp_abe_iclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> l4_cfg */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
.master = &omap44xx_l3_main_1_hwmod,
@ -988,8 +957,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l3_main_1__l3_main_3,
&omap44xx_l3_main_2__l3_main_3,
&omap44xx_l4_cfg__l3_main_3,
&omap44xx_l3_main_1__l4_abe,
&omap44xx_mpu__l4_abe,
&omap44xx_l3_main_1__l4_cfg,
&omap44xx_l3_main_2__l4_per,
&omap44xx_l4_cfg__l4_wkup,

31
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
View File

@ -121,19 +121,6 @@ static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
.name = "l4",
};
/* l4_abe */
static struct omap_hwmod omap54xx_l4_abe_hwmod = {
.name = "l4_abe",
.class = &omap54xx_l4_hwmod_class,
.clkdm_name = "abe_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
},
},
};
/* l4_cfg */
static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
.name = "l4_cfg",
@ -395,22 +382,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> l4_abe */
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
.master = &omap54xx_l3_main_1_hwmod,
.slave = &omap54xx_l4_abe_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* mpu -> l4_abe */
static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
.master = &omap54xx_mpu_hwmod,
.slave = &omap54xx_l4_abe_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> l4_cfg */
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
.master = &omap54xx_l3_main_1_hwmod,
@ -478,8 +449,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_l3_main_1__l3_main_3,
&omap54xx_l3_main_2__l3_main_3,
&omap54xx_l4_cfg__l3_main_3,
&omap54xx_l3_main_1__l4_abe,
&omap54xx_mpu__l4_abe,
&omap54xx_l3_main_1__l4_cfg,
&omap54xx_l3_main_2__l4_per,
&omap54xx_l3_main_1__l4_wkup,

44
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View File

@ -418,41 +418,6 @@ static struct omap_hwmod dra7xx_qspi_hwmod = {
},
};
/*
* 'rtcss' class
*
*/
static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
.rev_offs = 0x0074,
.sysc_offs = 0x0078,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type3,
};
static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
.name = "rtcss",
.sysc = &dra7xx_rtcss_sysc,
.unlock = &omap_hwmod_rtc_unlock,
.lock = &omap_hwmod_rtc_lock,
};
/* rtcss */
static struct omap_hwmod dra7xx_rtcss_hwmod = {
.name = "rtcss",
.class = &dra7xx_rtcss_hwmod_class,
.clkdm_name = "rtc_clkdm",
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'sata' class
*
@ -702,14 +667,6 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> rtcss */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_rtcss_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> sata */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
.master = &dra7xx_l4_cfg_hwmod,
@ -786,7 +743,6 @@ static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
};
static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per3__rtcss,
NULL,
};

25
arch/arm/mach-omap2/pm33xx-core.c
View File

@ -25,7 +25,6 @@
#include "control.h"
#include "clockdomain.h"
#include "iomap.h"
#include "omap_hwmod.h"
#include "pm.h"
#include "powerdomain.h"
#include "prm33xx.h"
@ -36,7 +35,6 @@
static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm;
static struct clockdomain *gfx_l4ls_clkdm;
static void __iomem *scu_base;
static struct omap_hwmod *rtc_oh;
static int (*idle_fn)(u32 wfi_flags);
@ -267,13 +265,6 @@ static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void)
return NULL;
}
static void __iomem *am43xx_get_rtc_base_addr(void)
{
rtc_oh = omap_hwmod_lookup("rtc");
return omap_hwmod_get_mpu_rt_va(rtc_oh);
}
static void am43xx_save_context(void)
{
}
@ -297,16 +288,6 @@ static void am43xx_restore_context(void)
writel_relaxed(0x0, AM33XX_L4_WK_IO_ADDRESS(0x44df2e14));
}
static void am43xx_prepare_rtc_suspend(void)
{
omap_hwmod_enable(rtc_oh);
}
static void am43xx_prepare_rtc_resume(void)
{
omap_hwmod_idle(rtc_oh);
}
static struct am33xx_pm_platform_data am33xx_ops = {
.init = am33xx_suspend_init,
.deinit = amx3_suspend_deinit,
@ -317,10 +298,7 @@ static struct am33xx_pm_platform_data am33xx_ops = {
.get_sram_addrs = amx3_get_sram_addrs,
.save_context = am33xx_save_context,
.restore_context = am33xx_restore_context,
.prepare_rtc_suspend = am43xx_prepare_rtc_suspend,
.prepare_rtc_resume = am43xx_prepare_rtc_resume,
.check_off_mode_enable = am33xx_check_off_mode_enable,
.get_rtc_base_addr = am43xx_get_rtc_base_addr,
};
static struct am33xx_pm_platform_data am43xx_ops = {
@ -333,10 +311,7 @@ static struct am33xx_pm_platform_data am43xx_ops = {
.get_sram_addrs = amx3_get_sram_addrs,
.save_context = am43xx_save_context,
.restore_context = am43xx_restore_context,
.prepare_rtc_suspend = am43xx_prepare_rtc_suspend,
.prepare_rtc_resume = am43xx_prepare_rtc_resume,
.check_off_mode_enable = am43xx_check_off_mode_enable,
.get_rtc_base_addr = am43xx_get_rtc_base_addr,
};
static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void)

274
drivers/soc/ti/omap_prm.c
View File

@ -10,14 +10,39 @@
#include <linux/device.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/reset-controller.h>
#include <linux/delay.h>
#include <linux/platform_data/ti-prm.h>
enum omap_prm_domain_mode {
OMAP_PRMD_OFF,
OMAP_PRMD_RETENTION,
OMAP_PRMD_ON_INACTIVE,
OMAP_PRMD_ON_ACTIVE,
};
struct omap_prm_domain_map {
unsigned int usable_modes; /* Mask of hardware supported modes */
unsigned long statechange:1; /* Optional low-power state change */
unsigned long logicretstate:1; /* Optional logic off mode */
};
struct omap_prm_domain {
struct device *dev;
struct omap_prm *prm;
struct generic_pm_domain pd;
u16 pwrstctrl;
u16 pwrstst;
const struct omap_prm_domain_map *cap;
u32 pwrstctrl_saved;
};
struct omap_rst_map {
s8 rst;
s8 st;
@ -27,6 +52,9 @@ struct omap_prm_data {
u32 base;
const char *name;
const char *clkdm_name;
u16 pwrstctrl;
u16 pwrstst;
const struct omap_prm_domain_map *dmap;
u16 rstctrl;
u16 rstst;
const struct omap_rst_map *rstmap;
@ -36,6 +64,7 @@ struct omap_prm_data {
struct omap_prm {
const struct omap_prm_data *data;
void __iomem *base;
struct omap_prm_domain *prmd;
};
struct omap_reset_data {
@ -47,6 +76,7 @@ struct omap_reset_data {
struct device *dev;
};
#define genpd_to_prm_domain(gpd) container_of(gpd, struct omap_prm_domain, pd)
#define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev)
#define OMAP_MAX_RESETS 8
@ -58,6 +88,39 @@ struct omap_reset_data {
#define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST)
#define PRM_STATE_MAX_WAIT 10000
#define PRM_LOGICRETSTATE BIT(2)
#define PRM_LOWPOWERSTATECHANGE BIT(4)
#define PRM_POWERSTATE_MASK OMAP_PRMD_ON_ACTIVE
#define PRM_ST_INTRANSITION BIT(20)
static const struct omap_prm_domain_map omap_prm_all = {
.usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_ON_INACTIVE) |
BIT(OMAP_PRMD_RETENTION) | BIT(OMAP_PRMD_OFF),
.statechange = 1,
.logicretstate = 1,
};
static const struct omap_prm_domain_map omap_prm_noinact = {
.usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_RETENTION) |
BIT(OMAP_PRMD_OFF),
.statechange = 1,
.logicretstate = 1,
};
static const struct omap_prm_domain_map omap_prm_nooff = {
.usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_ON_INACTIVE) |
BIT(OMAP_PRMD_RETENTION),
.statechange = 1,
.logicretstate = 1,
};
static const struct omap_prm_domain_map omap_prm_onoff_noauto = {
.usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_OFF),
.statechange = 1,
};
static const struct omap_rst_map rst_map_0[] = {
{ .rst = 0, .st = 0 },
{ .rst = -1 },
@ -78,6 +141,10 @@ static const struct omap_rst_map rst_map_012[] = {
static const struct omap_prm_data omap4_prm_data[] = {
{ .name = "tesla", .base = 0x4a306400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
{
.name = "abe", .base = 0x4a306500,
.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_all,
},
{ .name = "core", .base = 0x4a306700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati", .rstmap = rst_map_012 },
{ .name = "ivahd", .base = 0x4a306f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
{ .name = "device", .base = 0x4a307b00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
@ -86,6 +153,10 @@ static const struct omap_prm_data omap4_prm_data[] = {
static const struct omap_prm_data omap5_prm_data[] = {
{ .name = "dsp", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
{
.name = "abe", .base = 0x4ae06500,
.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_nooff,
},
{ .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu", .rstmap = rst_map_012 },
{ .name = "iva", .base = 0x4ae07200, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
{ .name = "device", .base = 0x4ae07c00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
@ -119,7 +190,11 @@ static const struct omap_prm_data am3_prm_data[] = {
{ .name = "per", .base = 0x44e00c00, .rstctrl = 0x0, .rstmap = am3_per_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL, .clkdm_name = "pruss_ocp" },
{ .name = "wkup", .base = 0x44e00d00, .rstctrl = 0x0, .rstst = 0xc, .rstmap = am3_wkup_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
{ .name = "device", .base = 0x44e00f00, .rstctrl = 0x0, .rstst = 0x8, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
{ .name = "gfx", .base = 0x44e01100, .rstctrl = 0x4, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3" },
{
.name = "gfx", .base = 0x44e01100,
.pwrstctrl = 0, .pwrstst = 0x10, .dmap = &omap_prm_noinact,
.rstctrl = 0x4, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3",
},
{ },
};
@ -135,7 +210,11 @@ static const struct omap_rst_map am4_device_rst_map[] = {
};
static const struct omap_prm_data am4_prm_data[] = {
{ .name = "gfx", .base = 0x44df0400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3" },
{
.name = "gfx", .base = 0x44df0400,
.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3",
},
{ .name = "per", .base = 0x44df0800, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am4_per_rst_map, .clkdm_name = "pruss_ocp" },
{ .name = "wkup", .base = 0x44df2000, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am3_wkup_rst_map, .flags = OMAP_PRM_HAS_NO_CLKDM },
{ .name = "device", .base = 0x44df4000, .rstctrl = 0x0, .rstst = 0x4, .rstmap = am4_device_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
@ -151,6 +230,180 @@ static const struct of_device_id omap_prm_id_table[] = {
{ },
};
#ifdef DEBUG
static void omap_prm_domain_show_state(struct omap_prm_domain *prmd,
const char *desc)
{
dev_dbg(prmd->dev, "%s %s: %08x/%08x\n",
prmd->pd.name, desc,
readl_relaxed(prmd->prm->base + prmd->pwrstctrl),
readl_relaxed(prmd->prm->base + prmd->pwrstst));
}
#else
static inline void omap_prm_domain_show_state(struct omap_prm_domain *prmd,
const char *desc)
{
}
#endif
static int omap_prm_domain_power_on(struct generic_pm_domain *domain)
{
struct omap_prm_domain *prmd;
int ret;
u32 v;
prmd = genpd_to_prm_domain(domain);
if (!prmd->cap)
return 0;
omap_prm_domain_show_state(prmd, "on: previous state");
if (prmd->pwrstctrl_saved)
v = prmd->pwrstctrl_saved;
else
v = readl_relaxed(prmd->prm->base + prmd->pwrstctrl);
writel_relaxed(v | OMAP_PRMD_ON_ACTIVE,
prmd->prm->base + prmd->pwrstctrl);
/* wait for the transition bit to get cleared */
ret = readl_relaxed_poll_timeout(prmd->prm->base + prmd->pwrstst,
v, !(v & PRM_ST_INTRANSITION), 1,
PRM_STATE_MAX_WAIT);
if (ret)
dev_err(prmd->dev, "%s: %s timed out\n",
prmd->pd.name, __func__);
omap_prm_domain_show_state(prmd, "on: new state");
return ret;
}
/* No need to check for holes in the mask for the lowest mode */
static int omap_prm_domain_find_lowest(struct omap_prm_domain *prmd)
{
return __ffs(prmd->cap->usable_modes);
}
static int omap_prm_domain_power_off(struct generic_pm_domain *domain)
{
struct omap_prm_domain *prmd;
int ret;
u32 v;
prmd = genpd_to_prm_domain(domain);
if (!prmd->cap)
return 0;
omap_prm_domain_show_state(prmd, "off: previous state");
v = readl_relaxed(prmd->prm->base + prmd->pwrstctrl);
prmd->pwrstctrl_saved = v;
v &= ~PRM_POWERSTATE_MASK;
v |= omap_prm_domain_find_lowest(prmd);
if (prmd->cap->statechange)
v |= PRM_LOWPOWERSTATECHANGE;
if (prmd->cap->logicretstate)
v &= ~PRM_LOGICRETSTATE;
else
v |= PRM_LOGICRETSTATE;
writel_relaxed(v, prmd->prm->base + prmd->pwrstctrl);
/* wait for the transition bit to get cleared */
ret = readl_relaxed_poll_timeout(prmd->prm->base + prmd->pwrstst,
v, !(v & PRM_ST_INTRANSITION), 1,
PRM_STATE_MAX_WAIT);
if (ret)
dev_warn(prmd->dev, "%s: %s timed out\n",
__func__, prmd->pd.name);
omap_prm_domain_show_state(prmd, "off: new state");
return 0;
}
static int omap_prm_domain_attach_dev(struct generic_pm_domain *domain,
struct device *dev)
{
struct generic_pm_domain_data *genpd_data;
struct of_phandle_args pd_args;
struct omap_prm_domain *prmd;
struct device_node *np;
int ret;
prmd = genpd_to_prm_domain(domain);
np = dev->of_node;
ret = of_parse_phandle_with_args(np, "power-domains",
"#power-domain-cells", 0, &pd_args);
if (ret < 0)
return ret;
if (pd_args.args_count != 0)
dev_warn(dev, "%s: unusupported #power-domain-cells: %i\n",
prmd->pd.name, pd_args.args_count);
genpd_data = dev_gpd_data(dev);
genpd_data->data = NULL;
return 0;
}
static void omap_prm_domain_detach_dev(struct generic_pm_domain *domain,
struct device *dev)
{
struct generic_pm_domain_data *genpd_data;
genpd_data = dev_gpd_data(dev);
genpd_data->data = NULL;
}
static int omap_prm_domain_init(struct device *dev, struct omap_prm *prm)
{
struct omap_prm_domain *prmd;
struct device_node *np = dev->of_node;
const struct omap_prm_data *data;
const char *name;
int error;
if (!of_find_property(dev->of_node, "#power-domain-cells", NULL))
return 0;
of_node_put(dev->of_node);
prmd = devm_kzalloc(dev, sizeof(*prmd), GFP_KERNEL);
if (!prmd)
return -ENOMEM;
data = prm->data;
name = devm_kasprintf(dev, GFP_KERNEL, "prm_%s",
data->name);
prmd->dev = dev;
prmd->prm = prm;
prmd->cap = prmd->prm->data->dmap;
prmd->pwrstctrl = prmd->prm->data->pwrstctrl;
prmd->pwrstst = prmd->prm->data->pwrstst;
prmd->pd.name = name;
prmd->pd.power_on = omap_prm_domain_power_on;
prmd->pd.power_off = omap_prm_domain_power_off;
prmd->pd.attach_dev = omap_prm_domain_attach_dev;
prmd->pd.detach_dev = omap_prm_domain_detach_dev;
pm_genpd_init(&prmd->pd, NULL, true);
error = of_genpd_add_provider_simple(np, &prmd->pd);
if (error)
pm_genpd_remove(&prmd->pd);
else
prm->prmd = prmd;
return error;
}
static bool _is_valid_reset(struct omap_reset_data *reset, unsigned long id)
{
if (reset->mask & BIT(id))
@ -351,6 +604,7 @@ static int omap_prm_probe(struct platform_device *pdev)
const struct omap_prm_data *data;
struct omap_prm *prm;
const struct of_device_id *match;
int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
@ -378,7 +632,21 @@ static int omap_prm_probe(struct platform_device *pdev)
if (IS_ERR(prm->base))
return PTR_ERR(prm->base);
return omap_prm_reset_init(pdev, prm);
ret = omap_prm_domain_init(&pdev->dev, prm);
if (ret)
return ret;
ret = omap_prm_reset_init(pdev, prm);
if (ret)
goto err_domain;
return 0;
err_domain:
of_genpd_del_provider(pdev->dev.of_node);
pm_genpd_remove(&prm->prmd->pd);
return ret;
}
static struct platform_driver omap_prm_driver = {

47
drivers/soc/ti/pm33xx.c
View File

@ -16,6 +16,7 @@
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_data/pm33xx.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
@ -39,6 +40,8 @@
#define GIC_INT_SET_PENDING_BASE 0x200
#define AM43XX_GIC_DIST_BASE 0x48241000
static void __iomem *rtc_base_virt;
static struct clk *rtc_fck;
static u32 rtc_magic_val;
static int (*am33xx_do_wfi_sram)(unsigned long unused);
@ -90,7 +93,7 @@ static int am33xx_push_sram_idle(void)
ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data;
ro_sram_data.amx3_pm_sram_data_phys =
gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data);
ro_sram_data.rtc_base_virt = pm_ops->get_rtc_base_addr();
ro_sram_data.rtc_base_virt = rtc_base_virt;
/* Save physical address to calculate resume offset during pm init */
am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool,
@ -158,7 +161,7 @@ static struct wkup_m3_wakeup_src rtc_wake_src(void)
{
u32 i;
i = __raw_readl(pm_ops->get_rtc_base_addr() + 0x44) & 0x40;
i = __raw_readl(rtc_base_virt + 0x44) & 0x40;
if (i) {
retrigger_irq = rtc_alarm_wakeup.irq_nr;
@ -177,13 +180,24 @@ static int am33xx_rtc_only_idle(unsigned long wfi_flags)
return 0;
}
/*
* Note that the RTC module clock must be re-enabled only for rtc+ddr suspend.
* And looks like the module can stay in SYSC_IDLE_SMART_WKUP mode configured
* by the interconnect code just fine for both rtc+ddr suspend and retention
* suspend.
*/
static int am33xx_pm_suspend(suspend_state_t suspend_state)
{
int i, ret = 0;
if (suspend_state == PM_SUSPEND_MEM &&
pm_ops->check_off_mode_enable()) {
pm_ops->prepare_rtc_suspend();
ret = clk_prepare_enable(rtc_fck);
if (ret) {
dev_err(pm33xx_dev, "Failed to enable clock: %i\n", ret);
return ret;
}
pm_ops->save_context();
suspend_wfi_flags |= WFI_FLAG_RTC_ONLY;
clk_save_context();
@ -236,7 +250,7 @@ static int am33xx_pm_suspend(suspend_state_t suspend_state)
}
if (suspend_state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable())
pm_ops->prepare_rtc_resume();
clk_disable_unprepare(rtc_fck);
return ret;
}
@ -425,14 +439,28 @@ static int am33xx_pm_rtc_setup(void)
struct device_node *np;
unsigned long val = 0;
struct nvmem_device *nvmem;
int error;
np = of_find_node_by_name(NULL, "rtc");
if (of_device_is_available(np)) {
/* RTC interconnect target module clock */
rtc_fck = of_clk_get_by_name(np->parent, "fck");
if (IS_ERR(rtc_fck))
return PTR_ERR(rtc_fck);
rtc_base_virt = of_iomap(np, 0);
if (!rtc_base_virt) {
pr_warn("PM: could not iomap rtc");
error = -ENODEV;
goto err_clk_put;
}
omap_rtc = rtc_class_open("rtc0");
if (!omap_rtc) {
pr_warn("PM: rtc0 not available");
return -EPROBE_DEFER;
error = -EPROBE_DEFER;
goto err_iounmap;
}
nvmem = devm_nvmem_device_get(&omap_rtc->dev,
@ -454,6 +482,13 @@ static int am33xx_pm_rtc_setup(void)
}
return 0;
err_iounmap:
iounmap(rtc_base_virt);
err_clk_put:
clk_put(rtc_fck);
return error;
}
static int am33xx_pm_probe(struct platform_device *pdev)
@ -544,6 +579,8 @@ static int am33xx_pm_remove(struct platform_device *pdev)
suspend_set_ops(NULL);
wkup_m3_ipc_put(m3_ipc);
am33xx_pm_free_sram();
iounmap(rtc_base_virt);
clk_put(rtc_fck);
return 0;
}

3
include/linux/platform_data/pm33xx.h
View File

@ -54,11 +54,8 @@ struct am33xx_pm_platform_data {
void (*begin_suspend)(void);
void (*finish_suspend)(void);
struct am33xx_pm_sram_addr *(*get_sram_addrs)(void);
void __iomem *(*get_rtc_base_addr)(void);
void (*save_context)(void);
void (*restore_context)(void);
void (*prepare_rtc_suspend)(void);
void (*prepare_rtc_resume)(void);
int (*check_off_mode_enable)(void);
};