drm/i915/tv: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain point in the register access macros I915_READ(), I915_WRITE(), POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW(). Replace them with the corresponding new display engine register accessors intel_de_read(), intel_de_write(), intel_de_posting_read(), intel_de_read_fw(), and intel_de_write_fw(). No functional changes. Generated using the following semantic patch: @@ expression REG, OFFSET; @@ - I915_READ(REG) + intel_de_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - POSTING_READ(REG) + intel_de_posting_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE(REG, OFFSET) + intel_de_write(dev_priv, REG, OFFSET) @@ expression REG; @@ - I915_READ_FW(REG) + intel_de_read_fw(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE_FW(REG, OFFSET) + intel_de_write_fw(dev_priv, REG, OFFSET) Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/6e6238e75f5a4155b1021736937b1fd7a0756a00.1579871655.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
d2afcc4441
commit
988ff27b58
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@ -907,7 +907,7 @@ static bool
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intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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u32 tmp = I915_READ(TV_CTL);
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u32 tmp = intel_de_read(dev_priv, TV_CTL);
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*pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
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@ -926,7 +926,8 @@ intel_enable_tv(struct intel_encoder *encoder,
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intel_wait_for_vblank(dev_priv,
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to_intel_crtc(pipe_config->uapi.crtc)->pipe);
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I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
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intel_de_write(dev_priv, TV_CTL,
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intel_de_read(dev_priv, TV_CTL) | TV_ENC_ENABLE);
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}
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static void
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@ -937,7 +938,8 @@ intel_disable_tv(struct intel_encoder *encoder,
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
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intel_de_write(dev_priv, TV_CTL,
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intel_de_read(dev_priv, TV_CTL) & ~TV_ENC_ENABLE);
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}
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static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)
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@ -1095,11 +1097,11 @@ intel_tv_get_config(struct intel_encoder *encoder,
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pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
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tv_ctl = I915_READ(TV_CTL);
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hctl1 = I915_READ(TV_H_CTL_1);
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hctl3 = I915_READ(TV_H_CTL_3);
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vctl1 = I915_READ(TV_V_CTL_1);
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vctl2 = I915_READ(TV_V_CTL_2);
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tv_ctl = intel_de_read(dev_priv, TV_CTL);
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hctl1 = intel_de_read(dev_priv, TV_H_CTL_1);
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hctl3 = intel_de_read(dev_priv, TV_H_CTL_3);
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vctl1 = intel_de_read(dev_priv, TV_V_CTL_1);
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vctl2 = intel_de_read(dev_priv, TV_V_CTL_2);
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tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT;
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tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT;
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@ -1134,11 +1136,11 @@ intel_tv_get_config(struct intel_encoder *encoder,
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break;
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}
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tmp = I915_READ(TV_WIN_POS);
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tmp = intel_de_read(dev_priv, TV_WIN_POS);
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xpos = tmp >> 16;
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ypos = tmp & 0xffff;
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tmp = I915_READ(TV_WIN_SIZE);
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tmp = intel_de_read(dev_priv, TV_WIN_SIZE);
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xsize = tmp >> 16;
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ysize = tmp & 0xffff;
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@ -1380,16 +1382,16 @@ set_tv_mode_timings(struct drm_i915_private *dev_priv,
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vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
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(tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
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I915_WRITE(TV_H_CTL_1, hctl1);
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I915_WRITE(TV_H_CTL_2, hctl2);
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I915_WRITE(TV_H_CTL_3, hctl3);
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I915_WRITE(TV_V_CTL_1, vctl1);
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I915_WRITE(TV_V_CTL_2, vctl2);
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I915_WRITE(TV_V_CTL_3, vctl3);
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I915_WRITE(TV_V_CTL_4, vctl4);
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I915_WRITE(TV_V_CTL_5, vctl5);
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I915_WRITE(TV_V_CTL_6, vctl6);
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I915_WRITE(TV_V_CTL_7, vctl7);
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intel_de_write(dev_priv, TV_H_CTL_1, hctl1);
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intel_de_write(dev_priv, TV_H_CTL_2, hctl2);
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intel_de_write(dev_priv, TV_H_CTL_3, hctl3);
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intel_de_write(dev_priv, TV_V_CTL_1, vctl1);
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intel_de_write(dev_priv, TV_V_CTL_2, vctl2);
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intel_de_write(dev_priv, TV_V_CTL_3, vctl3);
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intel_de_write(dev_priv, TV_V_CTL_4, vctl4);
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intel_de_write(dev_priv, TV_V_CTL_5, vctl5);
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intel_de_write(dev_priv, TV_V_CTL_6, vctl6);
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intel_de_write(dev_priv, TV_V_CTL_7, vctl7);
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}
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static void set_color_conversion(struct drm_i915_private *dev_priv,
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@ -1398,18 +1400,18 @@ static void set_color_conversion(struct drm_i915_private *dev_priv,
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if (!color_conversion)
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return;
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I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) |
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color_conversion->gy);
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I915_WRITE(TV_CSC_Y2, (color_conversion->by << 16) |
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color_conversion->ay);
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I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) |
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color_conversion->gu);
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I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) |
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color_conversion->au);
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I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) |
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color_conversion->gv);
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I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) |
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color_conversion->av);
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intel_de_write(dev_priv, TV_CSC_Y,
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(color_conversion->ry << 16) | color_conversion->gy);
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intel_de_write(dev_priv, TV_CSC_Y2,
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(color_conversion->by << 16) | color_conversion->ay);
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intel_de_write(dev_priv, TV_CSC_U,
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(color_conversion->ru << 16) | color_conversion->gu);
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intel_de_write(dev_priv, TV_CSC_U2,
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(color_conversion->bu << 16) | color_conversion->au);
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intel_de_write(dev_priv, TV_CSC_V,
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(color_conversion->rv << 16) | color_conversion->gv);
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intel_de_write(dev_priv, TV_CSC_V2,
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(color_conversion->bv << 16) | color_conversion->av);
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}
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static void intel_tv_pre_enable(struct intel_encoder *encoder,
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@ -1434,7 +1436,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
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if (!tv_mode)
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return; /* can't happen (mode_prepare prevents this) */
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tv_ctl = I915_READ(TV_CTL);
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tv_ctl = intel_de_read(dev_priv, TV_CTL);
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tv_ctl &= TV_CTL_SAVE;
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switch (intel_tv->type) {
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@ -1511,21 +1513,20 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
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set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
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I915_WRITE(TV_SC_CTL_1, scctl1);
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I915_WRITE(TV_SC_CTL_2, scctl2);
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I915_WRITE(TV_SC_CTL_3, scctl3);
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intel_de_write(dev_priv, TV_SC_CTL_1, scctl1);
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intel_de_write(dev_priv, TV_SC_CTL_2, scctl2);
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intel_de_write(dev_priv, TV_SC_CTL_3, scctl3);
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set_color_conversion(dev_priv, color_conversion);
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if (INTEL_GEN(dev_priv) >= 4)
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I915_WRITE(TV_CLR_KNOBS, 0x00404000);
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intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000);
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else
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I915_WRITE(TV_CLR_KNOBS, 0x00606000);
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intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000);
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if (video_levels)
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I915_WRITE(TV_CLR_LEVEL,
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((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
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(video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
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intel_de_write(dev_priv, TV_CLR_LEVEL,
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((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
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assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
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@ -1533,7 +1534,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
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tv_filter_ctl = TV_AUTO_SCALE;
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if (tv_conn_state->bypass_vfilter)
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tv_filter_ctl |= TV_V_FILTER_BYPASS;
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I915_WRITE(TV_FILTER_CTL_1, tv_filter_ctl);
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intel_de_write(dev_priv, TV_FILTER_CTL_1, tv_filter_ctl);
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xsize = tv_mode->hblank_start - tv_mode->hblank_end;
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ysize = intel_tv_mode_vdisplay(tv_mode);
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@ -1544,20 +1545,25 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
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conn_state->tv.margins.right);
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ysize -= (tv_conn_state->margins.top +
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tv_conn_state->margins.bottom);
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I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
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I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
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intel_de_write(dev_priv, TV_WIN_POS, (xpos << 16) | ypos);
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intel_de_write(dev_priv, TV_WIN_SIZE, (xsize << 16) | ysize);
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j = 0;
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for (i = 0; i < 60; i++)
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I915_WRITE(TV_H_LUMA(i), tv_mode->filter_table[j++]);
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intel_de_write(dev_priv, TV_H_LUMA(i),
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tv_mode->filter_table[j++]);
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for (i = 0; i < 60; i++)
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I915_WRITE(TV_H_CHROMA(i), tv_mode->filter_table[j++]);
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intel_de_write(dev_priv, TV_H_CHROMA(i),
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tv_mode->filter_table[j++]);
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for (i = 0; i < 43; i++)
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I915_WRITE(TV_V_LUMA(i), tv_mode->filter_table[j++]);
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intel_de_write(dev_priv, TV_V_LUMA(i),
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tv_mode->filter_table[j++]);
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for (i = 0; i < 43; i++)
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I915_WRITE(TV_V_CHROMA(i), tv_mode->filter_table[j++]);
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I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
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I915_WRITE(TV_CTL, tv_ctl);
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intel_de_write(dev_priv, TV_V_CHROMA(i),
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tv_mode->filter_table[j++]);
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intel_de_write(dev_priv, TV_DAC,
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intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE);
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intel_de_write(dev_priv, TV_CTL, tv_ctl);
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}
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static int
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@ -1581,8 +1587,8 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
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spin_unlock_irq(&dev_priv->irq_lock);
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}
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save_tv_dac = tv_dac = I915_READ(TV_DAC);
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save_tv_ctl = tv_ctl = I915_READ(TV_CTL);
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save_tv_dac = tv_dac = intel_de_read(dev_priv, TV_DAC);
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save_tv_ctl = tv_ctl = intel_de_read(dev_priv, TV_CTL);
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/* Poll for TV detection */
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tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK);
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@ -1608,14 +1614,14 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
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tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
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TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
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I915_WRITE(TV_CTL, tv_ctl);
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I915_WRITE(TV_DAC, tv_dac);
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POSTING_READ(TV_DAC);
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intel_de_write(dev_priv, TV_CTL, tv_ctl);
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intel_de_write(dev_priv, TV_DAC, tv_dac);
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intel_de_posting_read(dev_priv, TV_DAC);
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intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
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type = -1;
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tv_dac = I915_READ(TV_DAC);
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tv_dac = intel_de_read(dev_priv, TV_DAC);
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DRM_DEBUG_KMS("TV detected: %x, %x\n", tv_ctl, tv_dac);
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/*
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* A B C
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@ -1637,9 +1643,9 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
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type = -1;
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}
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I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
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I915_WRITE(TV_CTL, save_tv_ctl);
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POSTING_READ(TV_CTL);
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intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
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intel_de_write(dev_priv, TV_CTL, save_tv_ctl);
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intel_de_posting_read(dev_priv, TV_CTL);
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/* For unknown reasons the hw barfs if we don't do this vblank wait. */
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intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
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@ -1870,7 +1876,7 @@ intel_tv_init(struct drm_i915_private *dev_priv)
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int i, initial_mode = 0;
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struct drm_connector_state *state;
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if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
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if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
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return;
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if (!intel_bios_is_tv_present(dev_priv)) {
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@ -1882,15 +1888,15 @@ intel_tv_init(struct drm_i915_private *dev_priv)
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* Sanity check the TV output by checking to see if the
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* DAC register holds a value
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*/
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save_tv_dac = I915_READ(TV_DAC);
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save_tv_dac = intel_de_read(dev_priv, TV_DAC);
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I915_WRITE(TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
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tv_dac_on = I915_READ(TV_DAC);
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intel_de_write(dev_priv, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
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tv_dac_on = intel_de_read(dev_priv, TV_DAC);
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I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
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tv_dac_off = I915_READ(TV_DAC);
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intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
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tv_dac_off = intel_de_read(dev_priv, TV_DAC);
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I915_WRITE(TV_DAC, save_tv_dac);
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intel_de_write(dev_priv, TV_DAC, save_tv_dac);
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/*
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* If the register does not hold the state change enable
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