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drm/i915/audio: Unify register bit naming 

Rename a few g4x bits to match the ibx+ bits.

Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Cc: Takashi Iwai <tiwai@suse.de>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221026170150.2654-7-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä 2022-10-26 20:01:41 +03:00
parent 011aa42ef6
commit 985a74d8ec
2 changed files with 7 additions and 7 deletions
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10
drivers/gpu/drm/i915/display/intel_audio.c
View File

@ -340,7 +340,7 @@ static void g4x_audio_codec_disable(struct intel_encoder *encoder,
/* Invalidate ELD */
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
tmp &= ~G4X_ELDV;
tmp &= ~G4X_ELD_VALID;
intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
}
@ -355,13 +355,13 @@ static void g4x_audio_codec_enable(struct intel_encoder *encoder,
int len, i;
if (intel_eld_uptodate(connector,
G4X_AUD_CNTL_ST, G4X_ELDV,
G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
G4X_AUD_CNTL_ST, G4X_ELD_VALID,
G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK,
G4X_HDMIW_HDMIEDID))
return;
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
tmp &= ~(G4X_ELDV | G4X_ELD_ADDR_MASK);
tmp &= ~(G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK);
len = REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);
intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
@ -371,7 +371,7 @@ static void g4x_audio_codec_enable(struct intel_encoder *encoder,
*((const u32 *)eld + i));
tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
tmp |= G4X_ELDV;
tmp |= G4X_ELD_VALID;
intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
}

4
drivers/gpu/drm/i915/display/intel_audio_regs.h
View File

@ -9,9 +9,9 @@
#include "i915_reg_defs.h"
#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
#define G4X_ELDV REG_BIT(14)
#define G4X_ELD_VALID REG_BIT(14)
#define G4X_ELD_BUFFER_SIZE_MASK REG_GENMASK(13, 9)
#define G4X_ELD_ADDR_MASK REG_GENMASK(8, 5)
#define G4X_ELD_ADDRESS_MASK REG_GENMASK(8, 5)
#define G4X_ELD_ACK REG_BIT(4)
#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)