drm/msm/dpu: split SC8180X catalog entry to the separate file
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530842/ Link: https://lore.kernel.org/r/20230404130622.509628-17-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Dmitry Baryshkov
parent
2f36168e32
commit
97e2c80376
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_5_1_SC8180X_H
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#define _DPU_5_1_SC8180X_H
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static const struct dpu_caps sc8180x_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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.qseed_type = DPU_SSPP_SCALER_QSEED3,
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.has_src_split = true,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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.max_linewidth = 4096,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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.max_hdeci_exp = MAX_HORZ_DECIMATION,
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.max_vdeci_exp = MAX_VERT_DECIMATION,
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};
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static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = {
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.ubwc_version = DPU_HW_UBWC_VER_30,
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.highest_bank_bit = 0x3,
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};
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static const struct dpu_mdp_cfg sc8180x_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x45c,
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.features = BIT(DPU_MDP_AUDIO_SELECT),
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
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.clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
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.clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
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.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
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.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
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},
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};
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static const struct dpu_intf_cfg sc8180x_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
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INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
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INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
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/* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
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INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
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INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
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INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
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};
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static const struct dpu_perf_cfg sc8180x_perf_data = {
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.max_bw_low = 9600000,
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.max_bw_high = 9600000,
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.min_core_ib = 2400000,
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.min_llcc_ib = 800000,
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.min_dram_ib = 800000,
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.danger_lut_tbl = {0xf, 0xffff, 0x0},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc7180_qos_linear),
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.entries = sc7180_qos_linear
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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/* TODO: macrotile-qseed is different from macrotile */
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
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.caps = &sc8180x_dpu_caps,
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.ubwc = &sc8180x_ubwc_cfg,
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.mdp_count = ARRAY_SIZE(sc8180x_mdp),
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.mdp = sc8180x_mdp,
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.ctl_count = ARRAY_SIZE(sm8150_ctl),
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.ctl = sm8150_ctl,
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.sspp_count = ARRAY_SIZE(sdm845_sspp),
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.sspp = sdm845_sspp,
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.mixer_count = ARRAY_SIZE(sm8150_lm),
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.mixer = sm8150_lm,
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.pingpong_count = ARRAY_SIZE(sm8150_pp),
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.pingpong = sm8150_pp,
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.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
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.merge_3d = sm8150_merge_3d,
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.intf_count = ARRAY_SIZE(sc8180x_intf),
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.intf = sc8180x_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.reg_dma_count = 1,
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.dma_cfg = &sm8150_regdma,
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.perf = &sc8180x_perf_data,
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.mdss_irqs = IRQ_SC8180X_MASK,
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};
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#endif
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@ -361,20 +361,6 @@ static const struct dpu_caps sm8150_dpu_caps = {
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.max_vdeci_exp = MAX_VERT_DECIMATION,
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};
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static const struct dpu_caps sc8180x_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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.qseed_type = DPU_SSPP_SCALER_QSEED3,
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.has_src_split = true,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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.max_linewidth = 4096,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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.max_hdeci_exp = MAX_HORZ_DECIMATION,
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.max_vdeci_exp = MAX_VERT_DECIMATION,
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};
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static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = {
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.ubwc_version = DPU_HW_UBWC_VER_10,
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.highest_bank_bit = 0x2,
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@ -390,11 +376,6 @@ static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = {
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.highest_bank_bit = 0x2,
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};
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static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = {
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.ubwc_version = DPU_HW_UBWC_VER_30,
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.highest_bank_bit = 0x3,
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};
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static const struct dpu_mdp_cfg msm8998_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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@ -447,30 +428,6 @@ static const struct dpu_mdp_cfg sdm845_mdp[] = {
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},
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};
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static const struct dpu_mdp_cfg sc8180x_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x45C,
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.features = BIT(DPU_MDP_AUDIO_SELECT),
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
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.reg_off = 0x2AC, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
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.reg_off = 0x2B4, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG2] = {
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.reg_off = 0x2BC, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG3] = {
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.reg_off = 0x2C4, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
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.reg_off = 0x2AC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
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.reg_off = 0x2B4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
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.reg_off = 0x2BC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
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.reg_off = 0x2C4, .bit_off = 8},
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},
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};
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/*************************************************************
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* CTL sub blocks config
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*************************************************************/
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@ -1093,16 +1050,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
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INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
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};
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static const struct dpu_intf_cfg sc8180x_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
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INTF_BLK("intf_1", INTF_1, 0x6A800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
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INTF_BLK("intf_2", INTF_2, 0x6B000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
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/* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
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INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
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INTF_BLK("intf_4", INTF_4, 0x6C000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
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INTF_BLK("intf_5", INTF_5, 0x6C800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
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};
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/*************************************************************
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* Writeback blocks config
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*************************************************************/
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@ -1426,33 +1373,6 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_perf_cfg sc8180x_perf_data = {
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.max_bw_low = 9600000,
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.max_bw_high = 9600000,
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.min_core_ib = 2400000,
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.min_llcc_ib = 800000,
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.min_dram_ib = 800000,
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.danger_lut_tbl = {0xf, 0xffff, 0x0},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc7180_qos_linear),
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.entries = sc7180_qos_linear
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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/* TODO: macrotile-qseed is different from macrotile */
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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/*************************************************************
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* Hardware catalog
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*************************************************************/
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@ -1535,30 +1455,7 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
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.mdss_irqs = IRQ_SDM845_MASK,
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};
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static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
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.caps = &sc8180x_dpu_caps,
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.ubwc = &sc8180x_ubwc_cfg,
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.mdp_count = ARRAY_SIZE(sc8180x_mdp),
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.mdp = sc8180x_mdp,
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.ctl_count = ARRAY_SIZE(sm8150_ctl),
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.ctl = sm8150_ctl,
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.sspp_count = ARRAY_SIZE(sdm845_sspp),
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.sspp = sdm845_sspp,
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.mixer_count = ARRAY_SIZE(sm8150_lm),
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.mixer = sm8150_lm,
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.pingpong_count = ARRAY_SIZE(sm8150_pp),
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.pingpong = sm8150_pp,
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.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
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.merge_3d = sm8150_merge_3d,
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.intf_count = ARRAY_SIZE(sc8180x_intf),
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.intf = sc8180x_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.reg_dma_count = 1,
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.dma_cfg = &sm8150_regdma,
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.perf = &sc8180x_perf_data,
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.mdss_irqs = IRQ_SC8180X_MASK,
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};
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#include "catalog/dpu_5_1_sc8180x.h"
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#include "catalog/dpu_6_0_sm8250.h"
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#include "catalog/dpu_6_2_sc7180.h"
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