Merge branch 'next/soc-exynos5440' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
From Kukjin Kim: This is adding support for exynos5440, including Quad ARM Cortex-A15 cores and its reference board SSDK5440. Note, at this moment, just enabled minimal system part for initial kernel boot and pinctrl driver. * 'next/soc-exynos5440' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: dts: Add pin controller node for Samsung EXYNOS5440 SoC pinctrl: exynos5440: add pinctrl driver for Samsung EXYNOS5440 SoC ARM: dts: add initial dts file for EXYNOS5440, SSDK5440 ARM: EXYNOS: add support for EXYNOS5440 SoC Add/add conflict in arch/arm/boot/dts/Makefile. Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
97c0bd411c
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@ -24,7 +24,8 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
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dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
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exynos4210-smdkv310.dtb \
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exynos4210-trats.dtb \
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exynos5250-smdk5250.dtb
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exynos5250-smdk5250.dtb \
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exynos5440-ssdk5440.dtb
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dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
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ecx-2000.dtb
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dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
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@ -0,0 +1,46 @@
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/*
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* SAMSUNG SSDK5440 board device tree source
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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/include/ "exynos5440.dtsi"
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/ {
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model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
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compatible = "samsung,ssdk5440", "samsung,exynos5440";
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memory {
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reg = <0x80000000 0x80000000>;
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};
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chosen {
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bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC2,115200 init=/linuxrc";
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};
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spi {
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status = "disabled";
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};
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i2c@F0000 {
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status = "disabled";
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};
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i2c@100000 {
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status = "disabled";
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};
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watchdog {
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status = "disabled";
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};
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rtc {
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status = "disabled";
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};
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};
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@ -0,0 +1,159 @@
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/*
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* SAMSUNG EXYNOS5440 SoC device tree source
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "samsung,exynos5440";
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interrupt-parent = <&gic>;
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gic:interrupt-controller@2E0000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>;
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};
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cpus {
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cpu@0 {
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compatible = "arm,cortex-a15";
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>;
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clock-frequency = <1000000>;
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};
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};
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cpu@1 {
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compatible = "arm,cortex-a15";
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 14 0xf08>;
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clock-frequency = <1000000>;
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};
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};
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cpu@2 {
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compatible = "arm,cortex-a15";
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 14 0xf08>;
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clock-frequency = <1000000>;
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};
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};
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cpu@3 {
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compatible = "arm,cortex-a15";
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 14 0xf08>;
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clock-frequency = <1000000>;
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};
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};
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};
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common {
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compatible = "samsung,exynos5440";
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};
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serial@B0000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0xB0000 0x1000>;
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interrupts = <0 2 0>;
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};
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serial@C0000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0xC0000 0x1000>;
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interrupts = <0 3 0>;
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};
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spi {
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compatible = "samsung,exynos4210-spi";
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reg = <0xD0000 0x1000>;
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interrupts = <0 4 0>;
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tx-dma-channel = <&pdma0 5>; /* preliminary */
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rx-dma-channel = <&pdma0 4>; /* preliminary */
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#address-cells = <1>;
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#size-cells = <0>;
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};
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pinctrl {
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compatible = "samsung,pinctrl-exynos5440";
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reg = <0xE0000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#gpio-cells = <2>;
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fan: fan {
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samsung,exynos5440-pin-function = <1>;
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};
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hdd_led0: hdd_led0 {
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samsung,exynos5440-pin-function = <2>;
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};
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hdd_led1: hdd_led1 {
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samsung,exynos5440-pin-function = <3>;
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};
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uart1: uart1 {
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samsung,exynos5440-pin-function = <4>;
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};
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};
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i2c@F0000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0xF0000 0x1000>;
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interrupts = <0 5 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c@100000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x100000 0x1000>;
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interrupts = <0 6 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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watchdog {
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compatible = "samsung,s3c2410-wdt";
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reg = <0x110000 0x1000>;
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interrupts = <0 1 0>;
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};
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,amba-bus";
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interrupt-parent = <&gic>;
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ranges;
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pdma0: pdma@121A0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x120000 0x1000>;
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interrupts = <0 34 0>;
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};
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pdma1: pdma@121B0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x121000 0x1000>;
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interrupts = <0 35 0>;
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};
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};
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rtc {
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compatible = "samsung,s3c6410-rtc";
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reg = <0x130000 0x1000>;
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interrupts = <0 16 0>, <0 17 0>;
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};
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};
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@ -67,6 +67,15 @@ config SOC_EXYNOS5250
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help
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Enable EXYNOS5250 SoC support
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config SOC_EXYNOS5440
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bool "SAMSUNG EXYNOS5440"
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default y
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depends on ARCH_EXYNOS5
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select ARM_ARCH_TIMER
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select AUTO_ZRELADDR
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help
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Enable EXYNOS5440 SoC support
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config EXYNOS4_MCT
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bool
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default y
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@ -417,9 +426,9 @@ config MACH_EXYNOS4_DT
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config MACH_EXYNOS5_DT
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bool "SAMSUNG EXYNOS5 Machine using device tree"
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default y
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depends on ARCH_EXYNOS5
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select ARM_AMBA
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select SOC_EXYNOS5250
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select USE_OF
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help
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Machine support for Samsung EXYNOS5 machine with device tree enabled.
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@ -14,9 +14,9 @@ obj- :=
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obj-$(CONFIG_ARCH_EXYNOS) += common.o
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obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
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obj-$(CONFIG_ARCH_EXYNOS5) += clock-exynos5.o
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obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
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obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
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obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o
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obj-$(CONFIG_PM) += pm.o
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obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
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@ -58,9 +58,11 @@ static const char name_exynos4210[] = "EXYNOS4210";
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static const char name_exynos4212[] = "EXYNOS4212";
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static const char name_exynos4412[] = "EXYNOS4412";
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static const char name_exynos5250[] = "EXYNOS5250";
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static const char name_exynos5440[] = "EXYNOS5440";
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static void exynos4_map_io(void);
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static void exynos5_map_io(void);
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static void exynos5440_map_io(void);
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static void exynos4_init_clocks(int xtal);
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static void exynos5_init_clocks(int xtal);
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static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
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@ -99,6 +101,12 @@ static struct cpu_table cpu_ids[] __initdata = {
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.init_uarts = exynos_init_uarts,
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.init = exynos_init,
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.name = name_exynos5250,
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}, {
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.idcode = EXYNOS5440_SOC_ID,
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.idmask = EXYNOS5_SOC_MASK,
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.map_io = exynos5440_map_io,
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.init = exynos_init,
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.name = name_exynos5440,
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},
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};
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@ -113,6 +121,15 @@ static struct map_desc exynos_iodesc[] __initdata = {
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},
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};
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static struct map_desc exynos5440_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_CHIPID,
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.pfn = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc exynos4_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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@ -279,6 +296,15 @@ static struct map_desc exynos5_iodesc[] __initdata = {
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},
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};
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static struct map_desc exynos5440_iodesc0[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_UART,
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.pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
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.length = SZ_512K,
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.type = MT_DEVICE,
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},
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};
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void exynos4_restart(char mode, const char *cmd)
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{
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__raw_writel(0x1, S5P_SWRESET);
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@ -286,11 +312,29 @@ void exynos4_restart(char mode, const char *cmd)
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void exynos5_restart(char mode, const char *cmd)
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{
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__raw_writel(0x1, EXYNOS_SWRESET);
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u32 val;
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void __iomem *addr;
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if (of_machine_is_compatible("samsung,exynos5250")) {
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val = 0x1;
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addr = EXYNOS_SWRESET;
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} else if (of_machine_is_compatible("samsung,exynos5440")) {
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val = (0x10 << 20) | (0x1 << 16);
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addr = EXYNOS5440_SWRESET;
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} else {
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pr_err("%s: cannot support non-DT\n", __func__);
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return;
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}
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__raw_writel(val, addr);
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}
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void __init exynos_init_late(void)
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{
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if (of_machine_is_compatible("samsung,exynos5440"))
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/* to be supported later */
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return;
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exynos_pm_late_initcall();
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}
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@ -303,7 +347,11 @@ void __init exynos_init_late(void)
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void __init exynos_init_io(struct map_desc *mach_desc, int size)
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{
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/* initialize the io descriptors we need for initialization */
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iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
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if (of_machine_is_compatible("samsung,exynos5440"))
|
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iotable_init(exynos5440_iodesc, ARRAY_SIZE(exynos5440_iodesc));
|
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else
|
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iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
|
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|
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if (mach_desc)
|
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iotable_init(mach_desc, size);
|
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|
||||
|
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@ -389,6 +437,11 @@ static void __init exynos4_init_clocks(int xtal)
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exynos4_setup_clocks();
|
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}
|
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|
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static void __init exynos5440_map_io(void)
|
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{
|
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iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
|
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}
|
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|
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static void __init exynos5_init_clocks(int xtal)
|
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{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
|
@ -604,8 +657,9 @@ int __init combiner_of_init(struct device_node *np, struct device_node *parent)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id exynos4_dt_irq_match[] = {
|
||||
static const struct of_device_id exynos_dt_irq_match[] = {
|
||||
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
|
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{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
|
||||
{ .compatible = "samsung,exynos4210-combiner",
|
||||
.data = combiner_of_init, },
|
||||
{},
|
||||
|
|
@ -622,7 +676,7 @@ void __init exynos4_init_irq(void)
|
|||
gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
|
||||
#ifdef CONFIG_OF
|
||||
else
|
||||
of_irq_init(exynos4_dt_irq_match);
|
||||
of_irq_init(exynos_dt_irq_match);
|
||||
#endif
|
||||
|
||||
if (!of_have_populated_dt())
|
||||
|
|
@ -639,7 +693,7 @@ void __init exynos4_init_irq(void)
|
|||
void __init exynos5_init_irq(void)
|
||||
{
|
||||
#ifdef CONFIG_OF
|
||||
of_irq_init(exynos4_dt_irq_match);
|
||||
of_irq_init(exynos_dt_irq_match);
|
||||
#endif
|
||||
/*
|
||||
* The parameters of s5p_init_irq() are for VIC init.
|
||||
|
|
@ -669,7 +723,7 @@ static int __init exynos4_l2x0_cache_init(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
if (soc_is_exynos5250())
|
||||
if (soc_is_exynos5250() || soc_is_exynos5440())
|
||||
return 0;
|
||||
|
||||
ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
|
||||
|
|
@ -1010,6 +1064,8 @@ static int __init exynos_init_irq_eint(void)
|
|||
}
|
||||
}
|
||||
#endif
|
||||
if (soc_is_exynos5440())
|
||||
return 0;
|
||||
|
||||
if (soc_is_exynos5250())
|
||||
exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
|
||||
|
|
|
|||
|
|
@ -333,6 +333,11 @@
|
|||
#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
|
||||
#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
|
||||
|
||||
/* EXYNOS5440 */
|
||||
|
||||
#define EXYNOS5440_IRQ_UART0 IRQ_SPI(2)
|
||||
#define EXYNOS5440_IRQ_UART1 IRQ_SPI(3)
|
||||
|
||||
#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@
|
|||
#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
|
||||
|
||||
#define EXYNOS_PA_CHIPID 0x10000000
|
||||
#define EXYNOS5440_PA_CHIPID 0x00160000
|
||||
|
||||
#define EXYNOS4_PA_SYSCON 0x10010000
|
||||
#define EXYNOS5_PA_SYSCON 0x10050100
|
||||
|
|
@ -281,6 +282,10 @@
|
|||
#define EXYNOS5_PA_UART3 0x12C30000
|
||||
#define EXYNOS5_SZ_UART SZ_256
|
||||
|
||||
#define EXYNOS5440_PA_UART0 0x000B0000
|
||||
#define EXYNOS5440_PA_UART1 0x000C0000
|
||||
#define EXYNOS5440_SZ_UART SZ_256
|
||||
|
||||
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
|
||||
|
||||
#endif /* __ASM_ARCH_MAP_H */
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
|
||||
#define S5P_SWRESET S5P_PMUREG(0x0400)
|
||||
#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
|
||||
#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
|
||||
|
||||
#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
|
||||
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
|
||||
|
|
|
|||
|
|
@ -75,20 +75,33 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
|
|||
{},
|
||||
};
|
||||
|
||||
static void __init exynos5250_dt_map_io(void)
|
||||
static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
{},
|
||||
};
|
||||
|
||||
static void __init exynos5_dt_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
|
||||
if (of_machine_is_compatible("samsung,exynos5250"))
|
||||
s3c24xx_init_clocks(24000000);
|
||||
}
|
||||
|
||||
static void __init exynos5250_dt_machine_init(void)
|
||||
static void __init exynos5_dt_machine_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos5250_auxdata_lookup, NULL);
|
||||
if (of_machine_is_compatible("samsung,exynos5250"))
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos5250_auxdata_lookup, NULL);
|
||||
else if (of_machine_is_compatible("samsung,exynos5440"))
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos5440_auxdata_lookup, NULL);
|
||||
}
|
||||
|
||||
static char const *exynos5250_dt_compat[] __initdata = {
|
||||
static char const *exynos5_dt_compat[] __initdata = {
|
||||
"samsung,exynos5250",
|
||||
"samsung,exynos5440",
|
||||
NULL
|
||||
};
|
||||
|
||||
|
|
@ -96,11 +109,11 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
|
|||
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
|
||||
.init_irq = exynos5_init_irq,
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
.map_io = exynos5250_dt_map_io,
|
||||
.map_io = exynos5_dt_map_io,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = exynos5250_dt_machine_init,
|
||||
.init_machine = exynos5_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.timer = &exynos4_timer,
|
||||
.dt_compat = exynos5250_dt_compat,
|
||||
.dt_compat = exynos5_dt_compat,
|
||||
.restart = exynos5_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -19,7 +19,9 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/percpu.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <asm/arch_timer.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/localtimer.h>
|
||||
|
||||
|
|
@ -476,8 +478,13 @@ static void __init exynos4_timer_resources(void)
|
|||
#endif /* CONFIG_LOCAL_TIMERS */
|
||||
}
|
||||
|
||||
static void __init exynos4_timer_init(void)
|
||||
static void __init exynos_timer_init(void)
|
||||
{
|
||||
if (soc_is_exynos5440()) {
|
||||
arch_timer_of_register();
|
||||
return;
|
||||
}
|
||||
|
||||
if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
|
||||
mct_int_type = MCT_INT_SPI;
|
||||
else
|
||||
|
|
@ -489,5 +496,5 @@ static void __init exynos4_timer_init(void)
|
|||
}
|
||||
|
||||
struct sys_timer exynos4_timer = {
|
||||
.init = exynos4_timer_init,
|
||||
.init = exynos_timer_init,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ struct platform_device; /* don't need the contents */
|
|||
|
||||
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
if (soc_is_exynos5250())
|
||||
if (soc_is_exynos5250() || soc_is_exynos5440())
|
||||
/* will be implemented with gpio function */
|
||||
return;
|
||||
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@ extern unsigned long samsung_cpu_id;
|
|||
#define EXYNOS4_CPU_MASK 0xFFFE0000
|
||||
|
||||
#define EXYNOS5250_SOC_ID 0x43520000
|
||||
#define EXYNOS5440_SOC_ID 0x54400000
|
||||
#define EXYNOS5_SOC_MASK 0xFFFFF000
|
||||
|
||||
#define IS_SAMSUNG_CPU(name, id, mask) \
|
||||
|
|
@ -62,6 +63,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
|
|||
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
|
||||
IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
|
||||
|
||||
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
|
||||
defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
|
||||
|
|
@ -130,6 +132,12 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
|
|||
# define soc_is_exynos5250() 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5440)
|
||||
# define soc_is_exynos5440() is_samsung_exynos5440()
|
||||
#else
|
||||
# define soc_is_exynos5440() 0
|
||||
#endif
|
||||
|
||||
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
|
||||
|
||||
#ifndef KHZ
|
||||
|
|
|
|||
|
|
@ -188,6 +188,11 @@ config PINCTRL_EXYNOS4
|
|||
depends on OF && GPIOLIB
|
||||
select PINCTRL_SAMSUNG
|
||||
|
||||
config PINCTRL_EXYNOS5440
|
||||
bool "Samsung EXYNOS5440 SoC pinctrl driver"
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_MVEBU
|
||||
bool
|
||||
depends on ARCH_MVEBU
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@ obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
|
|||
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
|
||||
obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
|
||||
obj-$(CONFIG_PINCTRL_EXYNOS4) += pinctrl-exynos.o
|
||||
obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o
|
||||
obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
|
||||
obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
|
||||
obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,919 @@
|
|||
/*
|
||||
* pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
|
||||
*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
#include <linux/pinctrl/pinconf.h>
|
||||
#include "core.h"
|
||||
|
||||
/* EXYNOS5440 GPIO and Pinctrl register offsets */
|
||||
#define GPIO_MUX 0x00
|
||||
#define GPIO_IE 0x04
|
||||
#define GPIO_INT 0x08
|
||||
#define GPIO_TYPE 0x0C
|
||||
#define GPIO_VAL 0x10
|
||||
#define GPIO_OE 0x14
|
||||
#define GPIO_IN 0x18
|
||||
#define GPIO_PE 0x1C
|
||||
#define GPIO_PS 0x20
|
||||
#define GPIO_SR 0x24
|
||||
#define GPIO_DS0 0x28
|
||||
#define GPIO_DS1 0x2C
|
||||
|
||||
#define EXYNOS5440_MAX_PINS 23
|
||||
#define PIN_NAME_LENGTH 10
|
||||
|
||||
#define GROUP_SUFFIX "-grp"
|
||||
#define GSUFFIX_LEN sizeof(GROUP_SUFFIX)
|
||||
#define FUNCTION_SUFFIX "-mux"
|
||||
#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX)
|
||||
|
||||
/*
|
||||
* pin configuration type and its value are packed together into a 16-bits.
|
||||
* The upper 8-bits represent the configuration type and the lower 8-bits
|
||||
* hold the value of the configuration type.
|
||||
*/
|
||||
#define PINCFG_TYPE_MASK 0xFF
|
||||
#define PINCFG_VALUE_SHIFT 8
|
||||
#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
|
||||
#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
|
||||
#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
|
||||
#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
|
||||
PINCFG_VALUE_SHIFT)
|
||||
|
||||
/**
|
||||
* enum pincfg_type - possible pin configuration types supported.
|
||||
* @PINCFG_TYPE_PUD: Pull up/down configuration.
|
||||
* @PINCFG_TYPE_DRV: Drive strength configuration.
|
||||
* @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
|
||||
* @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
|
||||
*/
|
||||
enum pincfg_type {
|
||||
PINCFG_TYPE_PUD,
|
||||
PINCFG_TYPE_DRV,
|
||||
PINCFG_TYPE_SKEW_RATE,
|
||||
PINCFG_TYPE_INPUT_TYPE
|
||||
};
|
||||
|
||||
/**
|
||||
* struct exynos5440_pin_group: represent group of pins for pincfg setting.
|
||||
* @name: name of the pin group, used to lookup the group.
|
||||
* @pins: the pins included in this group.
|
||||
* @num_pins: number of pins included in this group.
|
||||
*/
|
||||
struct exynos5440_pin_group {
|
||||
const char *name;
|
||||
const unsigned int *pins;
|
||||
u8 num_pins;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct exynos5440_pmx_func: represent a pin function.
|
||||
* @name: name of the pin function, used to lookup the function.
|
||||
* @groups: one or more names of pin groups that provide this function.
|
||||
* @num_groups: number of groups included in @groups.
|
||||
* @function: the function number to be programmed when selected.
|
||||
*/
|
||||
struct exynos5440_pmx_func {
|
||||
const char *name;
|
||||
const char **groups;
|
||||
u8 num_groups;
|
||||
unsigned long function;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct exynos5440_pinctrl_priv_data: driver's private runtime data.
|
||||
* @reg_base: ioremapped based address of the register space.
|
||||
* @gc: gpio chip registered with gpiolib.
|
||||
* @pin_groups: list of pin groups parsed from device tree.
|
||||
* @nr_groups: number of pin groups available.
|
||||
* @pmx_functions: list of pin functions parsed from device tree.
|
||||
* @nr_functions: number of pin functions available.
|
||||
*/
|
||||
struct exynos5440_pinctrl_priv_data {
|
||||
void __iomem *reg_base;
|
||||
struct gpio_chip *gc;
|
||||
|
||||
const struct exynos5440_pin_group *pin_groups;
|
||||
unsigned int nr_groups;
|
||||
const struct exynos5440_pmx_func *pmx_functions;
|
||||
unsigned int nr_functions;
|
||||
};
|
||||
|
||||
/* list of all possible config options supported */
|
||||
struct pin_config {
|
||||
char *prop_cfg;
|
||||
unsigned int cfg_type;
|
||||
} pcfgs[] = {
|
||||
{ "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
|
||||
{ "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
|
||||
{ "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
|
||||
{ "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
|
||||
};
|
||||
|
||||
/* check if the selector is a valid pin group selector */
|
||||
static int exynos5440_get_group_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv;
|
||||
|
||||
priv = pinctrl_dev_get_drvdata(pctldev);
|
||||
return priv->nr_groups;
|
||||
}
|
||||
|
||||
/* return the name of the group selected by the group selector */
|
||||
static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev,
|
||||
unsigned selector)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv;
|
||||
|
||||
priv = pinctrl_dev_get_drvdata(pctldev);
|
||||
return priv->pin_groups[selector].name;
|
||||
}
|
||||
|
||||
/* return the pin numbers associated with the specified group */
|
||||
static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev,
|
||||
unsigned selector, const unsigned **pins, unsigned *num_pins)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv;
|
||||
|
||||
priv = pinctrl_dev_get_drvdata(pctldev);
|
||||
*pins = priv->pin_groups[selector].pins;
|
||||
*num_pins = priv->pin_groups[selector].num_pins;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* create pinctrl_map entries by parsing device tree nodes */
|
||||
static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct device_node *np, struct pinctrl_map **maps,
|
||||
unsigned *nmaps)
|
||||
{
|
||||
struct device *dev = pctldev->dev;
|
||||
struct pinctrl_map *map;
|
||||
unsigned long *cfg = NULL;
|
||||
char *gname, *fname;
|
||||
int cfg_cnt = 0, map_cnt = 0, idx = 0;
|
||||
|
||||
/* count the number of config options specfied in the node */
|
||||
for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++)
|
||||
if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
|
||||
cfg_cnt++;
|
||||
|
||||
/*
|
||||
* Find out the number of map entries to create. All the config options
|
||||
* can be accomadated into a single config map entry.
|
||||
*/
|
||||
if (cfg_cnt)
|
||||
map_cnt = 1;
|
||||
if (of_find_property(np, "samsung,exynos5440-pin-function", NULL))
|
||||
map_cnt++;
|
||||
if (!map_cnt) {
|
||||
dev_err(dev, "node %s does not have either config or function "
|
||||
"configurations\n", np->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Allocate memory for pin-map entries */
|
||||
map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
|
||||
if (!map) {
|
||||
dev_err(dev, "could not alloc memory for pin-maps\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
*nmaps = 0;
|
||||
|
||||
/*
|
||||
* Allocate memory for pin group name. The pin group name is derived
|
||||
* from the node name from which these map entries are be created.
|
||||
*/
|
||||
gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL);
|
||||
if (!gname) {
|
||||
dev_err(dev, "failed to alloc memory for group name\n");
|
||||
goto free_map;
|
||||
}
|
||||
sprintf(gname, "%s%s", np->name, GROUP_SUFFIX);
|
||||
|
||||
/*
|
||||
* don't have config options? then skip over to creating function
|
||||
* map entries.
|
||||
*/
|
||||
if (!cfg_cnt)
|
||||
goto skip_cfgs;
|
||||
|
||||
/* Allocate memory for config entries */
|
||||
cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
|
||||
if (!cfg) {
|
||||
dev_err(dev, "failed to alloc memory for configs\n");
|
||||
goto free_gname;
|
||||
}
|
||||
|
||||
/* Prepare a list of config settings */
|
||||
for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
|
||||
u32 value;
|
||||
if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
|
||||
cfg[cfg_cnt++] =
|
||||
PINCFG_PACK(pcfgs[idx].cfg_type, value);
|
||||
}
|
||||
|
||||
/* create the config map entry */
|
||||
map[*nmaps].data.configs.group_or_pin = gname;
|
||||
map[*nmaps].data.configs.configs = cfg;
|
||||
map[*nmaps].data.configs.num_configs = cfg_cnt;
|
||||
map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
|
||||
*nmaps += 1;
|
||||
|
||||
skip_cfgs:
|
||||
/* create the function map entry */
|
||||
if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
|
||||
fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL);
|
||||
if (!fname) {
|
||||
dev_err(dev, "failed to alloc memory for func name\n");
|
||||
goto free_cfg;
|
||||
}
|
||||
sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX);
|
||||
|
||||
map[*nmaps].data.mux.group = gname;
|
||||
map[*nmaps].data.mux.function = fname;
|
||||
map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
|
||||
*nmaps += 1;
|
||||
}
|
||||
|
||||
*maps = map;
|
||||
return 0;
|
||||
|
||||
free_cfg:
|
||||
kfree(cfg);
|
||||
free_gname:
|
||||
kfree(gname);
|
||||
free_map:
|
||||
kfree(map);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* free the memory allocated to hold the pin-map table */
|
||||
static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map *map, unsigned num_maps)
|
||||
{
|
||||
int idx;
|
||||
|
||||
for (idx = 0; idx < num_maps; idx++) {
|
||||
if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
|
||||
kfree(map[idx].data.mux.function);
|
||||
if (!idx)
|
||||
kfree(map[idx].data.mux.group);
|
||||
} else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
|
||||
kfree(map[idx].data.configs.configs);
|
||||
if (!idx)
|
||||
kfree(map[idx].data.configs.group_or_pin);
|
||||
}
|
||||
};
|
||||
|
||||
kfree(map);
|
||||
}
|
||||
|
||||
/* list of pinctrl callbacks for the pinctrl core */
|
||||
static struct pinctrl_ops exynos5440_pctrl_ops = {
|
||||
.get_groups_count = exynos5440_get_group_count,
|
||||
.get_group_name = exynos5440_get_group_name,
|
||||
.get_group_pins = exynos5440_get_group_pins,
|
||||
.dt_node_to_map = exynos5440_dt_node_to_map,
|
||||
.dt_free_map = exynos5440_dt_free_map,
|
||||
};
|
||||
|
||||
/* check if the selector is a valid pin function selector */
|
||||
static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv;
|
||||
|
||||
priv = pinctrl_dev_get_drvdata(pctldev);
|
||||
return priv->nr_functions;
|
||||
}
|
||||
|
||||
/* return the name of the pin function specified */
|
||||
static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev,
|
||||
unsigned selector)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv;
|
||||
|
||||
priv = pinctrl_dev_get_drvdata(pctldev);
|
||||
return priv->pmx_functions[selector].name;
|
||||
}
|
||||
|
||||
/* return the groups associated for the specified function selector */
|
||||
static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev,
|
||||
unsigned selector, const char * const **groups,
|
||||
unsigned * const num_groups)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv;
|
||||
|
||||
priv = pinctrl_dev_get_drvdata(pctldev);
|
||||
*groups = priv->pmx_functions[selector].groups;
|
||||
*num_groups = priv->pmx_functions[selector].num_groups;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* enable or disable a pinmux function */
|
||||
static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
|
||||
unsigned group, bool enable)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv;
|
||||
void __iomem *base;
|
||||
u32 function;
|
||||
u32 data;
|
||||
|
||||
priv = pinctrl_dev_get_drvdata(pctldev);
|
||||
base = priv->reg_base;
|
||||
function = priv->pmx_functions[selector].function;
|
||||
|
||||
data = readl(base + GPIO_MUX);
|
||||
if (enable)
|
||||
data |= (1 << function);
|
||||
else
|
||||
data &= ~(1 << function);
|
||||
writel(data, base + GPIO_MUX);
|
||||
}
|
||||
|
||||
/* enable a specified pinmux by writing to registers */
|
||||
static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
|
||||
unsigned group)
|
||||
{
|
||||
exynos5440_pinmux_setup(pctldev, selector, group, true);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* disable a specified pinmux by writing to registers */
|
||||
static void exynos5440_pinmux_disable(struct pinctrl_dev *pctldev,
|
||||
unsigned selector, unsigned group)
|
||||
{
|
||||
exynos5440_pinmux_setup(pctldev, selector, group, false);
|
||||
}
|
||||
|
||||
/*
|
||||
* The calls to gpio_direction_output() and gpio_direction_input()
|
||||
* leads to this function call (via the pinctrl_gpio_direction_{input|output}()
|
||||
* function called from the gpiolib interface).
|
||||
*/
|
||||
static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range, unsigned offset, bool input)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
|
||||
static struct pinmux_ops exynos5440_pinmux_ops = {
|
||||
.get_functions_count = exynos5440_get_functions_count,
|
||||
.get_function_name = exynos5440_pinmux_get_fname,
|
||||
.get_function_groups = exynos5440_pinmux_get_groups,
|
||||
.enable = exynos5440_pinmux_enable,
|
||||
.disable = exynos5440_pinmux_disable,
|
||||
.gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
|
||||
};
|
||||
|
||||
/* set the pin config settings for a specified pin */
|
||||
static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
unsigned long config)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv;
|
||||
void __iomem *base;
|
||||
enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(config);
|
||||
u32 cfg_value = PINCFG_UNPACK_VALUE(config);
|
||||
u32 data;
|
||||
|
||||
priv = pinctrl_dev_get_drvdata(pctldev);
|
||||
base = priv->reg_base;
|
||||
|
||||
switch (cfg_type) {
|
||||
case PINCFG_TYPE_PUD:
|
||||
/* first set pull enable/disable bit */
|
||||
data = readl(base + GPIO_PE);
|
||||
data &= ~(1 << pin);
|
||||
if (cfg_value)
|
||||
data |= (1 << pin);
|
||||
writel(data, base + GPIO_PE);
|
||||
|
||||
/* then set pull up/down bit */
|
||||
data = readl(base + GPIO_PS);
|
||||
data &= ~(1 << pin);
|
||||
if (cfg_value == 2)
|
||||
data |= (1 << pin);
|
||||
writel(data, base + GPIO_PS);
|
||||
break;
|
||||
|
||||
case PINCFG_TYPE_DRV:
|
||||
/* set the first bit of the drive strength */
|
||||
data = readl(base + GPIO_DS0);
|
||||
data &= ~(1 << pin);
|
||||
data |= ((cfg_value & 1) << pin);
|
||||
writel(data, base + GPIO_DS0);
|
||||
cfg_value >>= 1;
|
||||
|
||||
/* set the second bit of the driver strength */
|
||||
data = readl(base + GPIO_DS1);
|
||||
data &= ~(1 << pin);
|
||||
data |= ((cfg_value & 1) << pin);
|
||||
writel(data, base + GPIO_DS1);
|
||||
break;
|
||||
case PINCFG_TYPE_SKEW_RATE:
|
||||
data = readl(base + GPIO_SR);
|
||||
data &= ~(1 << pin);
|
||||
data |= ((cfg_value & 1) << pin);
|
||||
writel(data, base + GPIO_SR);
|
||||
break;
|
||||
case PINCFG_TYPE_INPUT_TYPE:
|
||||
data = readl(base + GPIO_TYPE);
|
||||
data &= ~(1 << pin);
|
||||
data |= ((cfg_value & 1) << pin);
|
||||
writel(data, base + GPIO_TYPE);
|
||||
break;
|
||||
default:
|
||||
WARN_ON(1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* get the pin config settings for a specified pin */
|
||||
static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
unsigned long *config)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv;
|
||||
void __iomem *base;
|
||||
enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
|
||||
u32 data;
|
||||
|
||||
priv = pinctrl_dev_get_drvdata(pctldev);
|
||||
base = priv->reg_base;
|
||||
|
||||
switch (cfg_type) {
|
||||
case PINCFG_TYPE_PUD:
|
||||
data = readl(base + GPIO_PE);
|
||||
data = (data >> pin) & 1;
|
||||
if (!data)
|
||||
*config = 0;
|
||||
else
|
||||
*config = ((readl(base + GPIO_PS) >> pin) & 1) + 1;
|
||||
break;
|
||||
case PINCFG_TYPE_DRV:
|
||||
data = readl(base + GPIO_DS0);
|
||||
data = (data >> pin) & 1;
|
||||
*config = data;
|
||||
data = readl(base + GPIO_DS1);
|
||||
data = (data >> pin) & 1;
|
||||
*config |= (data << 1);
|
||||
break;
|
||||
case PINCFG_TYPE_SKEW_RATE:
|
||||
data = readl(base + GPIO_SR);
|
||||
*config = (data >> pin) & 1;
|
||||
break;
|
||||
case PINCFG_TYPE_INPUT_TYPE:
|
||||
data = readl(base + GPIO_TYPE);
|
||||
*config = (data >> pin) & 1;
|
||||
break;
|
||||
default:
|
||||
WARN_ON(1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* set the pin config settings for a specified pin group */
|
||||
static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
|
||||
unsigned group, unsigned long config)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv;
|
||||
const unsigned int *pins;
|
||||
unsigned int cnt;
|
||||
|
||||
priv = pinctrl_dev_get_drvdata(pctldev);
|
||||
pins = priv->pin_groups[group].pins;
|
||||
|
||||
for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
|
||||
exynos5440_pinconf_set(pctldev, pins[cnt], config);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* get the pin config settings for a specified pin group */
|
||||
static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
|
||||
unsigned int group, unsigned long *config)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv;
|
||||
const unsigned int *pins;
|
||||
|
||||
priv = pinctrl_dev_get_drvdata(pctldev);
|
||||
pins = priv->pin_groups[group].pins;
|
||||
exynos5440_pinconf_get(pctldev, pins[0], config);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
|
||||
static struct pinconf_ops exynos5440_pinconf_ops = {
|
||||
.pin_config_get = exynos5440_pinconf_get,
|
||||
.pin_config_set = exynos5440_pinconf_set,
|
||||
.pin_config_group_get = exynos5440_pinconf_group_get,
|
||||
.pin_config_group_set = exynos5440_pinconf_group_set,
|
||||
};
|
||||
|
||||
/* gpiolib gpio_set callback function */
|
||||
static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
|
||||
void __iomem *base = priv->reg_base;
|
||||
u32 data;
|
||||
|
||||
data = readl(base + GPIO_VAL);
|
||||
data &= ~(1 << offset);
|
||||
if (value)
|
||||
data |= 1 << offset;
|
||||
writel(data, base + GPIO_VAL);
|
||||
}
|
||||
|
||||
/* gpiolib gpio_get callback function */
|
||||
static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
|
||||
void __iomem *base = priv->reg_base;
|
||||
u32 data;
|
||||
|
||||
data = readl(base + GPIO_IN);
|
||||
data >>= offset;
|
||||
data &= 1;
|
||||
return data;
|
||||
}
|
||||
|
||||
/* gpiolib gpio_direction_input callback function */
|
||||
static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
|
||||
void __iomem *base = priv->reg_base;
|
||||
u32 data;
|
||||
|
||||
/* first disable the data output enable on this pin */
|
||||
data = readl(base + GPIO_OE);
|
||||
data &= ~(1 << offset);
|
||||
writel(data, base + GPIO_OE);
|
||||
|
||||
/* now enable input on this pin */
|
||||
data = readl(base + GPIO_IE);
|
||||
data |= 1 << offset;
|
||||
writel(data, base + GPIO_IE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* gpiolib gpio_direction_output callback function */
|
||||
static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
|
||||
int value)
|
||||
{
|
||||
struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
|
||||
void __iomem *base = priv->reg_base;
|
||||
u32 data;
|
||||
|
||||
exynos5440_gpio_set(gc, offset, value);
|
||||
|
||||
/* first disable the data input enable on this pin */
|
||||
data = readl(base + GPIO_IE);
|
||||
data &= ~(1 << offset);
|
||||
writel(data, base + GPIO_IE);
|
||||
|
||||
/* now enable output on this pin */
|
||||
data = readl(base + GPIO_OE);
|
||||
data |= 1 << offset;
|
||||
writel(data, base + GPIO_OE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
|
||||
static int __init exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
|
||||
struct device_node *cfg_np, unsigned int **pin_list,
|
||||
unsigned int *npins)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct property *prop;
|
||||
|
||||
prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL);
|
||||
if (!prop)
|
||||
return -ENOENT;
|
||||
|
||||
*npins = prop->length / sizeof(unsigned long);
|
||||
if (!*npins) {
|
||||
dev_err(dev, "invalid pin list in %s node", cfg_np->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
*pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
|
||||
if (!*pin_list) {
|
||||
dev_err(dev, "failed to allocate memory for pin list\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
|
||||
*pin_list, *npins);
|
||||
}
|
||||
|
||||
/*
|
||||
* Parse the information about all the available pin groups and pin functions
|
||||
* from device node of the pin-controller.
|
||||
*/
|
||||
static int __init exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
|
||||
struct exynos5440_pinctrl_priv_data *priv)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *dev_np = dev->of_node;
|
||||
struct device_node *cfg_np;
|
||||
struct exynos5440_pin_group *groups, *grp;
|
||||
struct exynos5440_pmx_func *functions, *func;
|
||||
unsigned *pin_list;
|
||||
unsigned int npins, grp_cnt, func_idx = 0;
|
||||
char *gname, *fname;
|
||||
int ret;
|
||||
|
||||
grp_cnt = of_get_child_count(dev_np);
|
||||
if (!grp_cnt)
|
||||
return -EINVAL;
|
||||
|
||||
groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
|
||||
if (!groups) {
|
||||
dev_err(dev, "failed allocate memory for ping group list\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
grp = groups;
|
||||
|
||||
functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
|
||||
if (!functions) {
|
||||
dev_err(dev, "failed to allocate memory for function list\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
func = functions;
|
||||
|
||||
/*
|
||||
* Iterate over all the child nodes of the pin controller node
|
||||
* and create pin groups and pin function lists.
|
||||
*/
|
||||
for_each_child_of_node(dev_np, cfg_np) {
|
||||
u32 function;
|
||||
|
||||
ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np,
|
||||
&pin_list, &npins);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* derive pin group name from the node name */
|
||||
gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN,
|
||||
GFP_KERNEL);
|
||||
if (!gname) {
|
||||
dev_err(dev, "failed to alloc memory for group name\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX);
|
||||
|
||||
grp->name = gname;
|
||||
grp->pins = pin_list;
|
||||
grp->num_pins = npins;
|
||||
grp++;
|
||||
|
||||
ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function",
|
||||
&function);
|
||||
if (ret)
|
||||
continue;
|
||||
|
||||
/* derive function name from the node name */
|
||||
fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN,
|
||||
GFP_KERNEL);
|
||||
if (!fname) {
|
||||
dev_err(dev, "failed to alloc memory for func name\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX);
|
||||
|
||||
func->name = fname;
|
||||
func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
|
||||
if (!func->groups) {
|
||||
dev_err(dev, "failed to alloc memory for group list "
|
||||
"in pin function");
|
||||
return -ENOMEM;
|
||||
}
|
||||
func->groups[0] = gname;
|
||||
func->num_groups = 1;
|
||||
func->function = function;
|
||||
func++;
|
||||
func_idx++;
|
||||
}
|
||||
|
||||
priv->pin_groups = groups;
|
||||
priv->nr_groups = grp_cnt;
|
||||
priv->pmx_functions = functions;
|
||||
priv->nr_functions = func_idx;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* register the pinctrl interface with the pinctrl subsystem */
|
||||
static int __init exynos5440_pinctrl_register(struct platform_device *pdev,
|
||||
struct exynos5440_pinctrl_priv_data *priv)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct pinctrl_desc *ctrldesc;
|
||||
struct pinctrl_dev *pctl_dev;
|
||||
struct pinctrl_pin_desc *pindesc, *pdesc;
|
||||
struct pinctrl_gpio_range grange;
|
||||
char *pin_names;
|
||||
int pin, ret;
|
||||
|
||||
ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
|
||||
if (!ctrldesc) {
|
||||
dev_err(dev, "could not allocate memory for pinctrl desc\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ctrldesc->name = "exynos5440-pinctrl";
|
||||
ctrldesc->owner = THIS_MODULE;
|
||||
ctrldesc->pctlops = &exynos5440_pctrl_ops;
|
||||
ctrldesc->pmxops = &exynos5440_pinmux_ops;
|
||||
ctrldesc->confops = &exynos5440_pinconf_ops;
|
||||
|
||||
pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
|
||||
EXYNOS5440_MAX_PINS, GFP_KERNEL);
|
||||
if (!pindesc) {
|
||||
dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
ctrldesc->pins = pindesc;
|
||||
ctrldesc->npins = EXYNOS5440_MAX_PINS;
|
||||
|
||||
/* dynamically populate the pin number and pin name for pindesc */
|
||||
for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
|
||||
pdesc->number = pin;
|
||||
|
||||
/*
|
||||
* allocate space for storing the dynamically generated names for all
|
||||
* the pins which belong to this pin-controller.
|
||||
*/
|
||||
pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
|
||||
ctrldesc->npins, GFP_KERNEL);
|
||||
if (!pin_names) {
|
||||
dev_err(&pdev->dev, "mem alloc for pin names failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* for each pin, set the name of the pin */
|
||||
for (pin = 0; pin < ctrldesc->npins; pin++) {
|
||||
sprintf(pin_names, "gpio%02d", pin);
|
||||
pdesc = pindesc + pin;
|
||||
pdesc->name = pin_names;
|
||||
pin_names += PIN_NAME_LENGTH;
|
||||
}
|
||||
|
||||
ret = exynos5440_pinctrl_parse_dt(pdev, priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv);
|
||||
if (!pctl_dev) {
|
||||
dev_err(&pdev->dev, "could not register pinctrl driver\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
grange.name = "exynos5440-pctrl-gpio-range";
|
||||
grange.id = 0;
|
||||
grange.base = 0;
|
||||
grange.npins = EXYNOS5440_MAX_PINS;
|
||||
grange.gc = priv->gc;
|
||||
pinctrl_add_gpio_range(pctl_dev, &grange);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* register the gpiolib interface with the gpiolib subsystem */
|
||||
static int __init exynos5440_gpiolib_register(struct platform_device *pdev,
|
||||
struct exynos5440_pinctrl_priv_data *priv)
|
||||
{
|
||||
struct gpio_chip *gc;
|
||||
int ret;
|
||||
|
||||
gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
|
||||
if (!gc) {
|
||||
dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
priv->gc = gc;
|
||||
gc->base = 0;
|
||||
gc->ngpio = EXYNOS5440_MAX_PINS;
|
||||
gc->dev = &pdev->dev;
|
||||
gc->set = exynos5440_gpio_set;
|
||||
gc->get = exynos5440_gpio_get;
|
||||
gc->direction_input = exynos5440_gpio_direction_input;
|
||||
gc->direction_output = exynos5440_gpio_direction_output;
|
||||
gc->label = "gpiolib-exynos5440";
|
||||
gc->owner = THIS_MODULE;
|
||||
ret = gpiochip_add(gc);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
|
||||
"code: %d\n", gc->label, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* unregister the gpiolib interface with the gpiolib subsystem */
|
||||
static int __init exynos5440_gpiolib_unregister(struct platform_device *pdev,
|
||||
struct exynos5440_pinctrl_priv_data *priv)
|
||||
{
|
||||
int ret = gpiochip_remove(priv->gc);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "gpio chip remove failed\n");
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devinit exynos5440_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct exynos5440_pinctrl_priv_data *priv;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
if (!dev->of_node) {
|
||||
dev_err(dev, "device tree node not found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(priv), GFP_KERNEL);
|
||||
if (!priv) {
|
||||
dev_err(dev, "could not allocate memory for private data\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(dev, "cannot find IO resource\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
priv->reg_base = devm_request_and_ioremap(&pdev->dev, res);
|
||||
if (!priv->reg_base) {
|
||||
dev_err(dev, "ioremap failed\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = exynos5440_gpiolib_register(pdev, priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = exynos5440_pinctrl_register(pdev, priv);
|
||||
if (ret) {
|
||||
exynos5440_gpiolib_unregister(pdev, priv);
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, priv);
|
||||
dev_info(dev, "EXYNOS5440 pinctrl driver registered\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id exynos5440_pinctrl_dt_match[] = {
|
||||
{ .compatible = "samsung,exynos5440-pinctrl" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match);
|
||||
|
||||
static struct platform_driver exynos5440_pinctrl_driver = {
|
||||
.probe = exynos5440_pinctrl_probe,
|
||||
.driver = {
|
||||
.name = "exynos5440-pinctrl",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(exynos5440_pinctrl_dt_match),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init exynos5440_pinctrl_drv_register(void)
|
||||
{
|
||||
return platform_driver_register(&exynos5440_pinctrl_driver);
|
||||
}
|
||||
postcore_initcall(exynos5440_pinctrl_drv_register);
|
||||
|
||||
static void __exit exynos5440_pinctrl_drv_unregister(void)
|
||||
{
|
||||
platform_driver_unregister(&exynos5440_pinctrl_driver);
|
||||
}
|
||||
module_exit(exynos5440_pinctrl_drv_unregister);
|
||||
|
||||
MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
|
||||
MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -1646,7 +1646,8 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
|
||||
defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
|
||||
defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
|
||||
defined(CONFIG_SOC_EXYNOS5440)
|
||||
static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
|
||||
.info = &(struct s3c24xx_uart_info) {
|
||||
.name = "Samsung Exynos4 UART",
|
||||
|
|
|
|||
Loading…
Reference in New Issue