drm/amdgpu: update gc golden register for arcturus
Update golden setting to improve performance on HPC and ML apps Signed-off-by: shiwu.zhang <shiwu.zhang@amd.com> Tested-by: gang.long <gang.long@amd.com> Reviewed-by: guchun.chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -691,6 +691,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000)
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};
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static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = {
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