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ARM: dts: at91: use generic name for reset controller 

Use generic name for reset controller of AT91 devices to comply with
DT specifications.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220610092414.1816571-2-claudiu.beznea@microchip.com
This commit is contained in:
Claudiu Beznea 2022-06-10 12:24:06 +03:00
parent b66724d23d
commit 979813d2ab
11 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/at91sam9260.dtsi
View File

@ -123,7 +123,7 @@
clock-names = "slow_xtal", "main_xtal";
};
rstc@fffffd00 {
reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;

2
arch/arm/boot/dts/at91sam9261.dtsi
View File

@ -603,7 +603,7 @@
clock-names = "slow_xtal", "main_xtal";
};
rstc@fffffd00 {
reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&slow_xtal>;

2
arch/arm/boot/dts/at91sam9263.dtsi
View File

@ -151,7 +151,7 @@
clock-names = "t0_clk", "slow_clk";
};
rstc@fffffd00 {
reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&slow_xtal>;

2
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@ -137,7 +137,7 @@
clock-names = "slow_clk", "main_xtal";
};
rstc@fffffd00 {
reset-controller@fffffd00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;

2
arch/arm/boot/dts/at91sam9n12.dtsi
View File

@ -126,7 +126,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
};
rstc@fffffe00 {
reset-controller@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;

2
arch/arm/boot/dts/at91sam9rl.dtsi
View File

@ -766,7 +766,7 @@
clock-names = "slow_clk", "main_xtal";
};
rstc@fffffd00 {
reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;

2
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -134,7 +134,7 @@
clock-names = "slow_clk", "main_xtal";
};
reset_controller: rstc@fffffe00 {
reset_controller: reset-controller@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;

2
arch/arm/boot/dts/sam9x60.dtsi
View File

@ -667,7 +667,7 @@
clock-names = "td_slck", "md_slck", "main_xtal";
};
reset_controller: rstc@fffffe00 {
reset_controller: reset-controller@fffffe00 {
compatible = "microchip,sam9x60-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k 0>;

2
arch/arm/boot/dts/sama5d2.dtsi
View File

@ -668,7 +668,7 @@
ranges = <0 0xf8044000 0x1420>;
};
reset_controller: rstc@f8048000 {
reset_controller: reset-controller@f8048000 {
compatible = "atmel,sama5d3-rstc";
reg = <0xf8048000 0x10>;
clocks = <&clk32k>;

2
arch/arm/boot/dts/sama5d3.dtsi
View File

@ -1003,7 +1003,7 @@
clock-names = "slow_clk", "main_xtal";
};
reset_controller: rstc@fffffe00 {
reset_controller: reset-controller@fffffe00 {
compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;

2
arch/arm/boot/dts/sama5d4.dtsi
View File

@ -726,7 +726,7 @@
};
};
reset_controller: rstc@fc068600 {
reset_controller: reset-controller@fc068600 {
compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
reg = <0xfc068600 0x10>;
clocks = <&clk32k>;