drm/i915: Use bw state for per crtc SAGV evaluation
Future platforms require per-crtc SAGV evaluation and serializing global state when those are changed from different commits. v2: - Add has_sagv check to intel_crtc_can_enable_sagv so that it sets bit in reject mask. - Use bw_state in intel_pre/post_plane_enable_sagv instead of atomic state v3: - Fixed rebase conflict, now using intel_atomic_crtc_state_for_each_plane_state in order to call it from atomic check v4: - Use fb modifier from plane state v5: - Make intel_has_sagv static again(Ville) - Removed unnecessary NULL assignments(Ville) - Removed unnecessary SAGV debug(Ville) - Call intel_compute_sagv_mask only for modesets(Ville) - Serialize global state only if sagv results change, but not mask itself(Ville) v6: - use lock global state instead of serialize(Ville) v7: - use both global state lock and serialize depending on if we need to change only global state or access hw (Ville) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Cc: Ville Syrjälä <ville.syrjala@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200430191757.18206-1-stanislav.lisovskiy@intel.com
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@ -18,6 +18,12 @@ struct intel_crtc_state;
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struct intel_bw_state {
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struct intel_global_state base;
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/*
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* Contains a bit mask, used to determine, whether correspondent
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* pipe allows SAGV or not.
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*/
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u8 pipe_sagv_reject;
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unsigned int data_rate[I915_MAX_PIPES];
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u8 num_active_planes[I915_MAX_PIPES];
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};
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@ -43,6 +43,7 @@
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#include "i915_fixed.h"
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#include "i915_irq.h"
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#include "i915_trace.h"
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#include "display/intel_bw.h"
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#include "intel_pm.h"
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#include "intel_sideband.h"
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#include "../../../platform/x86/intel_ips.h"
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@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
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void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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const struct intel_bw_state *new_bw_state;
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if (!intel_can_enable_sagv(state))
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/*
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* Just return if we can't control SAGV or don't have it.
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* This is different from situation when we have SAGV but just can't
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* afford it due to DBuf limitation - in case if SAGV is completely
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* disabled in a BIOS, we are not even allowed to send a PCode request,
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* as it will throw an error. So have to check it here.
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*/
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if (!intel_has_sagv(dev_priv))
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return;
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new_bw_state = intel_atomic_get_new_bw_state(state);
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if (!new_bw_state)
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return;
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if (!intel_can_enable_sagv(new_bw_state))
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intel_disable_sagv(dev_priv);
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}
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void intel_sagv_post_plane_update(struct intel_atomic_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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const struct intel_bw_state *new_bw_state;
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if (intel_can_enable_sagv(state))
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/*
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* Just return if we can't control SAGV or don't have it.
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* This is different from situation when we have SAGV but just can't
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* afford it due to DBuf limitation - in case if SAGV is completely
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* disabled in a BIOS, we are not even allowed to send a PCode request,
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* as it will throw an error. So have to check it here.
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*/
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if (!intel_has_sagv(dev_priv))
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return;
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new_bw_state = intel_atomic_get_new_bw_state(state);
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if (!new_bw_state)
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return;
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if (intel_can_enable_sagv(new_bw_state))
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intel_enable_sagv(dev_priv);
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}
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static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc_state->uapi.crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_plane *plane;
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const struct intel_plane_state *plane_state;
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int level, latency;
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if (!intel_has_sagv(dev_priv))
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return false;
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if (!crtc_state->hw.active)
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return true;
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/*
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* SKL+ workaround: bspec recommends we disable SAGV when we have
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* more then one pipe enabled
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*/
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if (hweight8(state->active_pipes) > 1)
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return false;
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if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
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return false;
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for_each_intel_plane_on_crtc(dev, crtc, plane) {
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intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
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const struct skl_plane_wm *wm =
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&crtc_state->wm.skl.optimal.planes[plane->id];
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@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
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latency = dev_priv->wm.skl_latency[level];
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if (skl_needs_memory_bw_wa(dev_priv) &&
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plane->base.state->fb->modifier ==
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plane_state->uapi.fb->modifier ==
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I915_FORMAT_MOD_X_TILED)
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latency += 15;
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@ -3819,35 +3861,48 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
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return true;
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}
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bool intel_can_enable_sagv(struct intel_atomic_state *state)
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bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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return bw_state->pipe_sagv_reject == 0;
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}
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static int intel_compute_sagv_mask(struct intel_atomic_state *state)
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{
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int ret;
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struct intel_crtc *crtc;
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const struct intel_crtc_state *crtc_state;
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enum pipe pipe;
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struct intel_crtc_state *new_crtc_state;
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struct intel_bw_state *new_bw_state = NULL;
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const struct intel_bw_state *old_bw_state = NULL;
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int i;
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if (!intel_has_sagv(dev_priv))
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return false;
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for_each_new_intel_crtc_in_state(state, crtc,
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new_crtc_state, i) {
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new_bw_state = intel_atomic_get_bw_state(state);
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if (IS_ERR(new_bw_state))
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return PTR_ERR(new_bw_state);
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/*
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* If there are no active CRTCs, no additional checks need be performed
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*/
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if (hweight8(state->active_pipes) == 0)
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return true;
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old_bw_state = intel_atomic_get_old_bw_state(state);
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/*
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* SKL+ workaround: bspec recommends we disable SAGV when we have
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* more then one pipe enabled
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*/
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if (hweight8(state->active_pipes) > 1)
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return false;
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if (intel_crtc_can_enable_sagv(new_crtc_state))
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new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
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else
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new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
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}
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/* Since we're now guaranteed to only have one active CRTC... */
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pipe = ffs(state->active_pipes) - 1;
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crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
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crtc_state = to_intel_crtc_state(crtc->base.state);
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if (!new_bw_state)
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return 0;
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return intel_crtc_can_enable_sagv(crtc_state);
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if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
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ret = intel_atomic_serialize_global_state(&new_bw_state->base);
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if (ret)
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return ret;
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} else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
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ret = intel_atomic_lock_global_state(&new_bw_state->base);
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if (ret)
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return ret;
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}
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return 0;
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}
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/*
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@ -5811,6 +5866,12 @@ skl_compute_wm(struct intel_atomic_state *state)
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if (ret)
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return ret;
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if (state->modeset) {
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ret = intel_compute_sagv_mask(state);
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if (ret)
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return ret;
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}
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/*
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* skl_compute_ddb() will have adjusted the final watermarks
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* based on how much ddb is available. Now we can actually
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@ -9,6 +9,7 @@
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#include <linux/types.h>
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#include "i915_reg.h"
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#include "display/intel_bw.h"
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struct drm_device;
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struct drm_i915_private;
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@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
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struct skl_pipe_wm *out);
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void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
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void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
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bool intel_can_enable_sagv(struct intel_atomic_state *state);
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bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
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int intel_enable_sagv(struct drm_i915_private *dev_priv);
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int intel_disable_sagv(struct drm_i915_private *dev_priv);
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void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
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