drm/amdgpu/powerplay: add power up/down SDMA interfaces for renoir
1.Implement PowerUpSDMA/PowerDownSDMA interfaces in the swSMU for renoir 2.adjust smu ip block ahead of gfx&sdma ip block Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -760,10 +760,10 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
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amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
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if (is_support_sw_smu(adev))
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amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
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amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
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amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
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@ -1263,6 +1263,9 @@ static int smu_hw_init(void *handle)
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return ret;
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}
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if (adev->asic_type == CHIP_RENOIR)
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smu_powergate_sdma(&adev->smu, false);
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if (!smu->pm_enabled)
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return 0;
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@ -1310,6 +1313,9 @@ static int smu_hw_fini(void *handle)
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struct smu_table_context *table_context = &smu->smu_table;
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int ret = 0;
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if (adev->asic_type == CHIP_RENOIR)
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smu_powergate_sdma(&adev->smu, true);
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kfree(table_context->driver_pptable);
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table_context->driver_pptable = NULL;
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@ -473,6 +473,7 @@ struct smu_funcs
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int (*parse_pptable)(struct smu_context *smu);
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int (*populate_smc_pptable)(struct smu_context *smu);
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int (*check_fw_version)(struct smu_context *smu);
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int (*powergate_sdma)(struct smu_context *smu, bool gate);
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int (*write_pptable)(struct smu_context *smu);
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int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
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int (*set_tool_table_location)(struct smu_context *smu);
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@ -549,6 +550,8 @@ struct smu_funcs
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((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
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#define smu_setup_pptable(smu) \
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((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
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#define smu_powergate_sdma(smu, gate) \
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((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
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#define smu_get_vbios_bootup_values(smu) \
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((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
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#define smu_get_clk_info_from_vbios(smu) \
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@ -101,7 +101,6 @@ static int
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smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
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uint32_t param)
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{
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struct amdgpu_device *adev = smu->adev;
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int ret = 0, index = 0;
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@ -128,27 +127,55 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
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return ret;
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}
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static int smu_v12_0_check_fw_status(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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uint32_t mp1_fw_flags;
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mp1_fw_flags = RREG32_PCIE(MP1_Public |
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(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
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if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
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return 0;
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return -EIO;
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}
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static int smu_v12_0_check_fw_version(struct smu_context *smu)
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{
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uint32_t smu_version = 0xff;
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uint32_t smc_if_version = 0xff;
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int ret = 0;
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ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
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if (ret)
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goto err;
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ret = smu_read_smc_arg(smu, &smu_version);
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ret = smu_read_smc_arg(smu, &smc_if_version);
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if (ret)
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goto err;
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if (smu_version != smu->smc_if_version)
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if (smc_if_version != smu->smc_if_version)
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ret = -EINVAL;
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err:
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return ret;
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}
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static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
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{
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if (!(smu->adev->flags & AMD_IS_APU))
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return 0;
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if (gate)
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return smu_send_smc_msg(smu, SMU_MSG_PowerDownSdma);
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else
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return smu_send_smc_msg(smu, SMU_MSG_PowerUpSdma);
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}
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static const struct smu_funcs smu_v12_0_funcs = {
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.check_fw_status = smu_v12_0_check_fw_status,
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.check_fw_version = smu_v12_0_check_fw_version,
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.powergate_sdma = smu_v12_0_powergate_sdma,
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.send_smc_msg = smu_v12_0_send_msg,
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.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
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.read_smc_arg = smu_v12_0_read_arg,
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