iommu/vt-d: Use real PASID for flush in caching mode
If caching mode is supported, the hardware will cache none-present or erroneous translation entries. Hence, software should explicitly invalidate the PASID cache after a PASID table entry becomes present. We should issue such invalidation with the PASID value that we have changed. PASID 0 is not reserved for this case. Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Kevin Tian <kevin.tian@intel.com> Cc: Sankaran Rajesh <rajesh.sankaran@intel.com> Suggested-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Liu Yi L <yi.l.liu@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -423,17 +423,13 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_
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iommu->pasid_table[svm->pasid].val = pasid_entry_val;
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wmb();
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/* In caching mode, we still have to flush with PASID 0 when
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* a PASID table entry becomes present. Not entirely clear
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* *why* that would be the case — surely we could just issue
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* a flush with the PASID value that we've changed? The PASID
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* is the index into the table, after all. It's not like domain
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* IDs in the case of the equivalent context-entry change in
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* caching mode. And for that matter it's not entirely clear why
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* a VMM would be in the business of caching the PASID table
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* anyway. Surely that can be left entirely to the guest? */
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/*
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* Flush PASID cache when a PASID table entry becomes
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* present.
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*/
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if (cap_caching_mode(iommu->cap))
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intel_flush_pasid_dev(svm, sdev, 0);
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intel_flush_pasid_dev(svm, sdev, svm->pasid);
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}
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list_add_rcu(&sdev->list, &svm->devs);
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