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drm/amd/display: Add DMCU memory low power support 

[Why]
On some platforms, DMCU is no longer used. In these cases, some DMCU
memory should be completely powered off to save power.

[How]
1. Set DMCU_ERAM_MEM_PWR_FORCE to shutdown memory when DMCU is not in
   use
2. Added a debug option to allow this behaviour to be turned off
3. Set all memory low power debug options to off first, to not
   immediately cause problems

Signed-off-by: Jacky Liao <ziyu.liao@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jacky Liao 2020-10-21 17:31:26 -04:00 committed by Alex Deucher
parent 949c5cde3e
commit 96879ad3e4
3 changed files with 14 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -420,6 +420,8 @@ struct dc_bw_validation_profile {
union mem_low_power_enable_options {
struct {
bool i2c: 1;
bool dmcu: 1;
bool cm: 1;
bool mpc: 1;
bool optc: 1;
} bits;

7
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
View File

@ -597,6 +597,7 @@ struct dce_hwseq_registers {
uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
uint32_t HPO_TOP_CLOCK_CONTROL;
uint32_t ODM_MEM_PWR_CTRL3;
uint32_t DMU_MEM_PWR_CNTL;
};
/* set field name */
#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@ -836,7 +837,8 @@ struct dce_hwseq_registers {
HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh)
HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh)
#define HWSEQ_DCN301_MASK_SH_LIST(mask_sh)\
HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
@ -1046,7 +1048,8 @@ struct dce_hwseq_registers {
type D4VGA_MODE_ENABLE; \
type AZALIA_AUDIO_DTO_MODULE; \
type ODM_MEM_UNASSIGNED_PWR_MODE; \
type ODM_MEM_VBLANK_PWR_MODE;
type ODM_MEM_VBLANK_PWR_MODE; \
type DMCU_ERAM_MEM_PWR_FORCE;
#define HWSEQ_DCN3_REG_FIELD_LIST(type) \
type HPO_HDMISTREAMCLK_GATE_DIS;

7
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
View File

@ -462,6 +462,13 @@ void dcn30_init_hw(struct dc *dc)
hws->funcs.disable_vga(dc->hwseq);
}
if (dc->debug.enable_mem_low_power.bits.dmcu) {
// Force ERAM to shutdown if DMCU is not enabled
if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
}
}
// Set default OPTC memory power states
if (dc->debug.enable_mem_low_power.bits.optc) {
// Shutdown when unassigned and light sleep in VBLANK