mmc: mmci: Add Qualcomm specific register defines.
This patch adds a Qualcomm SD Card controller specific register variations to header file. Qualcomm SDCC controller is pl180, with slight changes in the register layout from standard pl180 register set. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -41,6 +41,15 @@
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/* Modified PL180 on Versatile Express platform */
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#define MCI_ARM_HWFCEN (1 << 12)
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/* Modified on Qualcomm Integrations */
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#define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11))
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#define MCI_QCOM_CLK_FLOWENA BIT(12)
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#define MCI_QCOM_CLK_INVERTOUT BIT(13)
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/* select in latch data and command in */
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#define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15)
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#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15))
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#define MMCIARGUMENT 0x008
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#define MMCICOMMAND 0x00c
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#define MCI_CPSM_RESPONSE (1 << 6)
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@ -54,6 +63,14 @@
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#define MCI_ST_NIEN (1 << 13)
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#define MCI_ST_CE_ATACMD (1 << 14)
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/* Modified on Qualcomm Integrations */
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#define MCI_QCOM_CSPM_DATCMD BIT(12)
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#define MCI_QCOM_CSPM_MCIABORT BIT(13)
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#define MCI_QCOM_CSPM_CCSENABLE BIT(14)
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#define MCI_QCOM_CSPM_CCSDISABLE BIT(15)
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#define MCI_QCOM_CSPM_AUTO_CMD19 BIT(16)
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#define MCI_QCOM_CSPM_AUTO_CMD21 BIT(21)
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#define MMCIRESPCMD 0x010
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#define MMCIRESPONSE0 0x014
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#define MMCIRESPONSE1 0x018
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