drm/i915/gen9: fix PIPE_CONTROL flush for VS_INVALIDATE
On GEN9+ per specification a NULL PIPE_CONTROL needs to be emitted before any PIPE_CONTROL command with the VS_INVALIDATE flag set. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1262,6 +1262,7 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
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{
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struct intel_engine_cs *ring = ringbuf->ring;
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u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
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bool vf_flush_wa;
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u32 flags = 0;
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int ret;
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@ -1283,10 +1284,26 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
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flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
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}
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ret = intel_logical_ring_begin(ringbuf, ctx, 6);
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/*
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* On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
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* control.
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*/
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vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
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flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
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ret = intel_logical_ring_begin(ringbuf, ctx, vf_flush_wa ? 12 : 6);
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if (ret)
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return ret;
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if (vf_flush_wa) {
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intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
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intel_logical_ring_emit(ringbuf, 0);
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intel_logical_ring_emit(ringbuf, 0);
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intel_logical_ring_emit(ringbuf, 0);
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intel_logical_ring_emit(ringbuf, 0);
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intel_logical_ring_emit(ringbuf, 0);
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}
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intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
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intel_logical_ring_emit(ringbuf, flags);
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intel_logical_ring_emit(ringbuf, scratch_addr);
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