tg3: Pure code movement.
This patch moves some functions towards the top of the file to avoid unnecessary function prototypes. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
5406460098
commit
95e2869adc
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@ -804,6 +804,243 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
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return ret;
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}
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static int tg3_bmcr_reset(struct tg3 *tp)
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{
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u32 phy_control;
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int limit, err;
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/* OK, reset it, and poll the BMCR_RESET bit until it
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* clears or we time out.
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*/
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phy_control = BMCR_RESET;
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err = tg3_writephy(tp, MII_BMCR, phy_control);
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if (err != 0)
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return -EBUSY;
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limit = 5000;
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while (limit--) {
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err = tg3_readphy(tp, MII_BMCR, &phy_control);
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if (err != 0)
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return -EBUSY;
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if ((phy_control & BMCR_RESET) == 0) {
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udelay(40);
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break;
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}
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udelay(10);
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}
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if (limit <= 0)
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return -EBUSY;
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return 0;
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}
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/* tp->lock is held. */
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static void tg3_wait_for_event_ack(struct tg3 *tp)
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{
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int i;
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/* Wait for up to 2.5 milliseconds */
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for (i = 0; i < 250000; i++) {
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if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
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break;
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udelay(10);
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}
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}
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/* tp->lock is held. */
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static void tg3_ump_link_report(struct tg3 *tp)
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{
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u32 reg;
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u32 val;
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if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
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!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
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return;
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tg3_wait_for_event_ack(tp);
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
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val = 0;
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if (!tg3_readphy(tp, MII_BMCR, ®))
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val = reg << 16;
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if (!tg3_readphy(tp, MII_BMSR, ®))
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val |= (reg & 0xffff);
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
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val = 0;
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if (!tg3_readphy(tp, MII_ADVERTISE, ®))
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val = reg << 16;
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if (!tg3_readphy(tp, MII_LPA, ®))
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val |= (reg & 0xffff);
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
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val = 0;
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if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
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if (!tg3_readphy(tp, MII_CTRL1000, ®))
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val = reg << 16;
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if (!tg3_readphy(tp, MII_STAT1000, ®))
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val |= (reg & 0xffff);
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}
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
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if (!tg3_readphy(tp, MII_PHYADDR, ®))
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val = reg << 16;
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else
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val = 0;
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
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val = tr32(GRC_RX_CPU_EVENT);
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val |= GRC_RX_CPU_DRIVER_EVENT;
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tw32_f(GRC_RX_CPU_EVENT, val);
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}
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static void tg3_link_report(struct tg3 *tp)
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{
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if (!netif_carrier_ok(tp->dev)) {
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if (netif_msg_link(tp))
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printk(KERN_INFO PFX "%s: Link is down.\n",
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tp->dev->name);
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tg3_ump_link_report(tp);
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} else if (netif_msg_link(tp)) {
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printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
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tp->dev->name,
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(tp->link_config.active_speed == SPEED_1000 ?
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1000 :
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(tp->link_config.active_speed == SPEED_100 ?
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100 : 10)),
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(tp->link_config.active_duplex == DUPLEX_FULL ?
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"full" : "half"));
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printk(KERN_INFO PFX
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"%s: Flow control is %s for TX and %s for RX.\n",
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tp->dev->name,
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(tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
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"on" : "off",
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(tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
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"on" : "off");
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tg3_ump_link_report(tp);
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}
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}
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static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
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{
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u16 miireg;
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if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
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miireg = ADVERTISE_PAUSE_CAP;
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else if (flow_ctrl & TG3_FLOW_CTRL_TX)
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miireg = ADVERTISE_PAUSE_ASYM;
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else if (flow_ctrl & TG3_FLOW_CTRL_RX)
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miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
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else
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miireg = 0;
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return miireg;
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}
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static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
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{
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u16 miireg;
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if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
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miireg = ADVERTISE_1000XPAUSE;
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else if (flow_ctrl & TG3_FLOW_CTRL_TX)
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miireg = ADVERTISE_1000XPSE_ASYM;
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else if (flow_ctrl & TG3_FLOW_CTRL_RX)
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miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
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else
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miireg = 0;
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return miireg;
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}
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static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
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{
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u8 cap = 0;
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if (lcladv & ADVERTISE_PAUSE_CAP) {
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if (lcladv & ADVERTISE_PAUSE_ASYM) {
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if (rmtadv & LPA_PAUSE_CAP)
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cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
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else if (rmtadv & LPA_PAUSE_ASYM)
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cap = TG3_FLOW_CTRL_RX;
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} else {
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if (rmtadv & LPA_PAUSE_CAP)
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cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
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}
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} else if (lcladv & ADVERTISE_PAUSE_ASYM) {
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if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
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cap = TG3_FLOW_CTRL_TX;
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}
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return cap;
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}
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static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
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{
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u8 cap = 0;
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if (lcladv & ADVERTISE_1000XPAUSE) {
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if (lcladv & ADVERTISE_1000XPSE_ASYM) {
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if (rmtadv & LPA_1000XPAUSE)
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cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
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else if (rmtadv & LPA_1000XPAUSE_ASYM)
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cap = TG3_FLOW_CTRL_RX;
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} else {
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if (rmtadv & LPA_1000XPAUSE)
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cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
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}
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} else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
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if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
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cap = TG3_FLOW_CTRL_TX;
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}
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return cap;
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}
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static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
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{
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u8 new_tg3_flags = 0;
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u32 old_rx_mode = tp->rx_mode;
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u32 old_tx_mode = tp->tx_mode;
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if (tp->link_config.autoneg == AUTONEG_ENABLE &&
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(tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
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if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
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new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv,
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remote_adv);
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else
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new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv,
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remote_adv);
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} else {
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new_tg3_flags = tp->link_config.flowctrl;
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}
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tp->link_config.active_flowctrl = new_tg3_flags;
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if (new_tg3_flags & TG3_FLOW_CTRL_RX)
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tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
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else
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tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
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if (old_rx_mode != tp->rx_mode) {
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tw32_f(MAC_RX_MODE, tp->rx_mode);
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}
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if (new_tg3_flags & TG3_FLOW_CTRL_TX)
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tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
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else
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tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
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if (old_tx_mode != tp->tx_mode) {
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tw32_f(MAC_TX_MODE, tp->tx_mode);
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}
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}
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static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
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{
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
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@ -861,37 +1098,6 @@ static void tg3_phy_set_wirespeed(struct tg3 *tp)
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(val | (1 << 15) | (1 << 4)));
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}
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static int tg3_bmcr_reset(struct tg3 *tp)
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{
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u32 phy_control;
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int limit, err;
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/* OK, reset it, and poll the BMCR_RESET bit until it
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* clears or we time out.
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*/
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phy_control = BMCR_RESET;
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err = tg3_writephy(tp, MII_BMCR, phy_control);
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if (err != 0)
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return -EBUSY;
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limit = 5000;
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while (limit--) {
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err = tg3_readphy(tp, MII_BMCR, &phy_control);
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if (err != 0)
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return -EBUSY;
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if ((phy_control & BMCR_RESET) == 0) {
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udelay(40);
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break;
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}
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udelay(10);
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}
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if (limit <= 0)
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return -EBUSY;
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return 0;
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}
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static void tg3_phy_apply_otp(struct tg3 *tp)
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{
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u32 otp, phy;
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@ -1115,8 +1321,6 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
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return err;
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}
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static void tg3_link_report(struct tg3 *);
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/* This will reset the tigon3 PHY if there is no valid
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* link unless the FORCE argument is non-zero.
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*/
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@ -1656,212 +1860,6 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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return 0;
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}
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/* tp->lock is held. */
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static void tg3_wait_for_event_ack(struct tg3 *tp)
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{
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int i;
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/* Wait for up to 2.5 milliseconds */
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for (i = 0; i < 250000; i++) {
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if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
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break;
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udelay(10);
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}
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}
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/* tp->lock is held. */
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static void tg3_ump_link_report(struct tg3 *tp)
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{
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u32 reg;
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u32 val;
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if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
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!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
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return;
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tg3_wait_for_event_ack(tp);
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
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val = 0;
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if (!tg3_readphy(tp, MII_BMCR, ®))
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val = reg << 16;
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if (!tg3_readphy(tp, MII_BMSR, ®))
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val |= (reg & 0xffff);
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
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val = 0;
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if (!tg3_readphy(tp, MII_ADVERTISE, ®))
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val = reg << 16;
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if (!tg3_readphy(tp, MII_LPA, ®))
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val |= (reg & 0xffff);
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
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val = 0;
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if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
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if (!tg3_readphy(tp, MII_CTRL1000, ®))
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val = reg << 16;
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if (!tg3_readphy(tp, MII_STAT1000, ®))
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val |= (reg & 0xffff);
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}
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
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if (!tg3_readphy(tp, MII_PHYADDR, ®))
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val = reg << 16;
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else
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val = 0;
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
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val = tr32(GRC_RX_CPU_EVENT);
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val |= GRC_RX_CPU_DRIVER_EVENT;
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tw32_f(GRC_RX_CPU_EVENT, val);
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}
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static void tg3_link_report(struct tg3 *tp)
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{
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if (!netif_carrier_ok(tp->dev)) {
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if (netif_msg_link(tp))
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printk(KERN_INFO PFX "%s: Link is down.\n",
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tp->dev->name);
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tg3_ump_link_report(tp);
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} else if (netif_msg_link(tp)) {
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printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
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tp->dev->name,
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(tp->link_config.active_speed == SPEED_1000 ?
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1000 :
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(tp->link_config.active_speed == SPEED_100 ?
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100 : 10)),
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(tp->link_config.active_duplex == DUPLEX_FULL ?
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"full" : "half"));
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printk(KERN_INFO PFX
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"%s: Flow control is %s for TX and %s for RX.\n",
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tp->dev->name,
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(tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
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"on" : "off",
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(tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
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"on" : "off");
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tg3_ump_link_report(tp);
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}
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}
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static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
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{
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u16 miireg;
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if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
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miireg = ADVERTISE_PAUSE_CAP;
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else if (flow_ctrl & TG3_FLOW_CTRL_TX)
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miireg = ADVERTISE_PAUSE_ASYM;
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else if (flow_ctrl & TG3_FLOW_CTRL_RX)
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miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
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else
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miireg = 0;
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return miireg;
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}
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static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
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{
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u16 miireg;
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if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
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miireg = ADVERTISE_1000XPAUSE;
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else if (flow_ctrl & TG3_FLOW_CTRL_TX)
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miireg = ADVERTISE_1000XPSE_ASYM;
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else if (flow_ctrl & TG3_FLOW_CTRL_RX)
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miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
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else
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miireg = 0;
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return miireg;
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}
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static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
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{
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u8 cap = 0;
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if (lcladv & ADVERTISE_PAUSE_CAP) {
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if (lcladv & ADVERTISE_PAUSE_ASYM) {
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if (rmtadv & LPA_PAUSE_CAP)
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cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
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else if (rmtadv & LPA_PAUSE_ASYM)
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cap = TG3_FLOW_CTRL_RX;
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} else {
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if (rmtadv & LPA_PAUSE_CAP)
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cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
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}
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} else if (lcladv & ADVERTISE_PAUSE_ASYM) {
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if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
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||||
cap = TG3_FLOW_CTRL_TX;
|
||||
}
|
||||
|
||||
return cap;
|
||||
}
|
||||
|
||||
static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
|
||||
{
|
||||
u8 cap = 0;
|
||||
|
||||
if (lcladv & ADVERTISE_1000XPAUSE) {
|
||||
if (lcladv & ADVERTISE_1000XPSE_ASYM) {
|
||||
if (rmtadv & LPA_1000XPAUSE)
|
||||
cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
|
||||
else if (rmtadv & LPA_1000XPAUSE_ASYM)
|
||||
cap = TG3_FLOW_CTRL_RX;
|
||||
} else {
|
||||
if (rmtadv & LPA_1000XPAUSE)
|
||||
cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
|
||||
}
|
||||
} else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
|
||||
if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
|
||||
cap = TG3_FLOW_CTRL_TX;
|
||||
}
|
||||
|
||||
return cap;
|
||||
}
|
||||
|
||||
static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
|
||||
{
|
||||
u8 new_tg3_flags = 0;
|
||||
u32 old_rx_mode = tp->rx_mode;
|
||||
u32 old_tx_mode = tp->tx_mode;
|
||||
|
||||
if (tp->link_config.autoneg == AUTONEG_ENABLE &&
|
||||
(tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
|
||||
if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
|
||||
new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv,
|
||||
remote_adv);
|
||||
else
|
||||
new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv,
|
||||
remote_adv);
|
||||
} else {
|
||||
new_tg3_flags = tp->link_config.flowctrl;
|
||||
}
|
||||
|
||||
tp->link_config.active_flowctrl = new_tg3_flags;
|
||||
|
||||
if (new_tg3_flags & TG3_FLOW_CTRL_RX)
|
||||
tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
|
||||
else
|
||||
tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
|
||||
|
||||
if (old_rx_mode != tp->rx_mode) {
|
||||
tw32_f(MAC_RX_MODE, tp->rx_mode);
|
||||
}
|
||||
|
||||
if (new_tg3_flags & TG3_FLOW_CTRL_TX)
|
||||
tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
|
||||
else
|
||||
tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
|
||||
|
||||
if (old_tx_mode != tp->tx_mode) {
|
||||
tw32_f(MAC_TX_MODE, tp->tx_mode);
|
||||
}
|
||||
}
|
||||
|
||||
static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
|
||||
{
|
||||
switch (val & MII_TG3_AUX_STAT_SPDMASK) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue