drm/i915/pxp: Implement arb session teardown
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. Additionally, we want to emit a
teardown operation to make sure we're clean on boot and resume
v2: emit in the ring, use high prio request (Chris)
v3: better defines, stalling flush, cleaned up and renamed submission
funcs (Chris)
v12: fix uninitialized variable bug
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210924191452.1539378-9-alan.previn.teres.alexis@intel.com
This commit is contained in:
Huang, Sean Z
Rodrigo Vivi
parent
cbbd3764b2
commit
95c9e1224d
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@ -281,6 +281,7 @@ i915-y += i915_perf.o
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# Protected execution platform (PXP) support
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i915-$(CONFIG_DRM_I915_PXP) += \
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pxp/intel_pxp.o \
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pxp/intel_pxp_cmd.o \
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pxp/intel_pxp_session.o \
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pxp/intel_pxp_tee.o
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@ -28,10 +28,13 @@
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#define INSTR_26_TO_24_MASK 0x7000000
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#define INSTR_26_TO_24_SHIFT 24
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#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
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/*
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* Memory interface instructions used by the kernel
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*/
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#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
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#define MI_INSTR(opcode, flags) \
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(__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
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/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
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#define MI_GLOBAL_GTT (1<<22)
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@ -57,6 +60,7 @@
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#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
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#define MI_SUSPEND_FLUSH_EN (1<<0)
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#define MI_SET_APPID MI_INSTR(0x0e, 0)
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#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
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#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
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#define MI_OVERLAY_CONTINUE (0x0<<21)
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#define MI_OVERLAY_ON (0x1<<21)
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@ -146,6 +150,7 @@
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#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
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#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
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#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
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#define MI_FLUSH_DW_PROTECTED_MEM_EN (1 << 22)
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#define MI_FLUSH_DW_STORE_INDEX (1<<21)
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#define MI_INVALIDATE_TLB (1<<18)
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#define MI_FLUSH_DW_OP_STOREDW (1<<14)
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@ -272,6 +277,19 @@
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#define MI_MATH_REG_ZF 0x32
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#define MI_MATH_REG_CF 0x33
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/*
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* Media instructions used by the kernel
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*/
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#define MEDIA_INSTR(pipe, op, sub_op, flags) \
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(__INSTR(INSTR_RC_CLIENT) | (pipe) << INSTR_SUBCLIENT_SHIFT | \
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(op) << INSTR_26_TO_24_SHIFT | (sub_op) << 16 | (flags))
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#define MFX_WAIT MEDIA_INSTR(1, 0, 0, 0)
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#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG REG_BIT(8)
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#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG REG_BIT(9)
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#define CRYPTO_KEY_EXCHANGE MEDIA_INSTR(2, 6, 9, 0)
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/*
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* Commands used only by the command parser
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*/
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@ -328,8 +346,6 @@
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#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
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((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
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#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
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#define COLOR_BLT ((0x2<<29)|(0x40<<22))
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#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
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@ -110,9 +110,14 @@ void intel_pxp_fini(struct intel_pxp *pxp)
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void intel_pxp_init_hw(struct intel_pxp *pxp)
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{
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int ret;
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kcr_pxp_enable(pxp_to_gt(pxp));
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intel_pxp_create_arb_session(pxp);
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/* always emit a full termination to clean the state */
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ret = intel_pxp_terminate_arb_session_and_global(pxp);
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if (!ret)
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intel_pxp_create_arb_session(pxp);
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}
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void intel_pxp_fini_hw(struct intel_pxp *pxp)
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@ -0,0 +1,141 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright(c) 2020, Intel Corporation. All rights reserved.
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*/
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#include "intel_pxp.h"
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#include "intel_pxp_cmd.h"
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#include "intel_pxp_session.h"
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#include "gt/intel_context.h"
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#include "gt/intel_engine_pm.h"
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#include "gt/intel_gpu_commands.h"
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#include "gt/intel_ring.h"
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#include "i915_trace.h"
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/* stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
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#define MFX_WAIT_PXP (MFX_WAIT | \
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MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | \
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MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG)
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static u32 *pxp_emit_session_selection(u32 *cs, u32 idx)
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{
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*cs++ = MFX_WAIT_PXP;
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/* pxp off */
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*cs++ = MI_FLUSH_DW;
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*cs++ = 0;
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*cs++ = 0;
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/* select session */
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*cs++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx);
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*cs++ = MFX_WAIT_PXP;
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/* pxp on */
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*cs++ = MI_FLUSH_DW | MI_FLUSH_DW_PROTECTED_MEM_EN |
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MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
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*cs++ = I915_GEM_HWS_PXP_ADDR | MI_FLUSH_DW_USE_GTT;
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*cs++ = 0;
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*cs++ = MFX_WAIT_PXP;
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return cs;
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}
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static u32 *pxp_emit_inline_termination(u32 *cs)
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{
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/* session inline termination */
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*cs++ = CRYPTO_KEY_EXCHANGE;
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*cs++ = 0;
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return cs;
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}
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static u32 *pxp_emit_session_termination(u32 *cs, u32 idx)
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{
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cs = pxp_emit_session_selection(cs, idx);
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cs = pxp_emit_inline_termination(cs);
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return cs;
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}
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static u32 *pxp_emit_wait(u32 *cs)
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{
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/* wait for cmds to go through */
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*cs++ = MFX_WAIT_PXP;
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*cs++ = 0;
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return cs;
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}
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/*
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* if we ever need to terminate more than one session, we can submit multiple
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* selections and terminations back-to-back with a single wait at the end
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*/
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#define SELECTION_LEN 10
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#define TERMINATION_LEN 2
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#define SESSION_TERMINATION_LEN(x) ((SELECTION_LEN + TERMINATION_LEN) * (x))
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#define WAIT_LEN 2
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static void pxp_request_commit(struct i915_request *rq)
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{
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struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX };
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struct intel_timeline * const tl = i915_request_timeline(rq);
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lockdep_unpin_lock(&tl->mutex, rq->cookie);
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trace_i915_request_add(rq);
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__i915_request_commit(rq);
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__i915_request_queue(rq, &attr);
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mutex_unlock(&tl->mutex);
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}
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int intel_pxp_terminate_session(struct intel_pxp *pxp, u32 id)
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{
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struct i915_request *rq;
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struct intel_context *ce = pxp->ce;
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u32 *cs;
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int err = 0;
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if (!intel_pxp_is_enabled(pxp))
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return 0;
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rq = i915_request_create(ce);
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if (IS_ERR(rq))
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return PTR_ERR(rq);
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if (ce->engine->emit_init_breadcrumb) {
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err = ce->engine->emit_init_breadcrumb(rq);
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if (err)
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goto out_rq;
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}
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cs = intel_ring_begin(rq, SESSION_TERMINATION_LEN(1) + WAIT_LEN);
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if (IS_ERR(cs)) {
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err = PTR_ERR(cs);
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goto out_rq;
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}
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cs = pxp_emit_session_termination(cs, id);
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cs = pxp_emit_wait(cs);
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intel_ring_advance(rq, cs);
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out_rq:
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i915_request_get(rq);
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if (unlikely(err))
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i915_request_set_error_once(rq, err);
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pxp_request_commit(rq);
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if (!err && i915_request_wait(rq, 0, HZ / 5) < 0)
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err = -ETIME;
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i915_request_put(rq);
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return err;
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}
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@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright(c) 2020, Intel Corporation. All rights reserved.
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*/
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#ifndef __INTEL_PXP_CMD_H__
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#define __INTEL_PXP_CMD_H__
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#include <linux/types.h>
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struct intel_pxp;
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int intel_pxp_terminate_session(struct intel_pxp *pxp, u32 idx);
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#endif /* __INTEL_PXP_CMD_H__ */
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@ -7,6 +7,7 @@
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#include "i915_drv.h"
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#include "intel_pxp.h"
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#include "intel_pxp_cmd.h"
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#include "intel_pxp_session.h"
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#include "intel_pxp_tee.h"
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#include "intel_pxp_types.h"
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@ -15,6 +16,9 @@
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#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
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/* PXP global terminate register for session termination */
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#define PXP_GLOBAL_TERMINATE _MMIO(0x320f8)
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static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
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{
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struct intel_gt *gt = pxp_to_gt(pxp);
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@ -72,3 +76,28 @@ int intel_pxp_create_arb_session(struct intel_pxp *pxp)
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return 0;
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}
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int intel_pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
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{
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int ret;
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struct intel_gt *gt = pxp_to_gt(pxp);
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pxp->arb_is_valid = false;
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/* terminate the hw sessions */
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ret = intel_pxp_terminate_session(pxp, ARB_SESSION);
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if (ret) {
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drm_err(>->i915->drm, "Failed to submit session termination\n");
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return ret;
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}
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ret = pxp_wait_for_session_state(pxp, ARB_SESSION, false);
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if (ret) {
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drm_err(>->i915->drm, "Session state did not clear\n");
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return ret;
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}
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intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1);
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return ret;
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}
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@ -11,5 +11,6 @@
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struct intel_pxp;
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int intel_pxp_create_arb_session(struct intel_pxp *pxp);
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int intel_pxp_terminate_arb_session_and_global(struct intel_pxp *pxp);
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#endif /* __INTEL_PXP_SESSION_H__ */
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