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MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WA 

Previously, in cpu_probe_ingenic(), c->writecombine was set to
_CACHE_UNCACHED_ACCELERATED, but this macro was defined differently when
CONFIG_MACH_INGENIC was set. This made it impossible to support multiple
CPUs.

Address this issue by setting c->writecombine to _CACHE_CACHABLE_WA
directly and removing the dependency on CONFIG_MACH_INGENIC.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Paul Cercueil 2020-09-06 21:29:22 +02:00 committed by Thomas Bogendoerfer
parent 7487abbe85
commit 95b1f6db67
2 changed files with 2 additions and 6 deletions
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5
arch/mips/include/asm/pgtable-bits.h
View File

@ -249,11 +249,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
#elif defined(CONFIG_MACH_INGENIC)
/* Ingenic uses the WA bit to achieve write-combine memory writes */
#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_NO_WA

3
arch/mips/kernel/cpu-probe.c
View File

@ -2169,8 +2169,9 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
/* XBurst®1 with MXU2.0 SIMD ISA */
case PRID_IMP_XBURST_REV2:
/* Ingenic uses the WA bit to achieve write-combine memory writes */
c->writecombine = _CACHE_CACHABLE_WA;
c->cputype = CPU_XBURST;
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
__cpu_name[cpu] = "Ingenic XBurst";
break;