Merge branch 'pci/ctrl/aardvark'
- Add support for AER capability on emulated bridge (Pali Rohár) - Add support for Slot capability on emulated bridge (Pali Rohár) * pci/ctrl/aardvark: PCI: aardvark: Fix reporting Slot capabilities on emulated bridge PCI: aardvark: Add support for AER registers on emulated bridge
This commit is contained in:
Bjorn Helgaas
commit
95aa832bd2
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@ -8,6 +8,7 @@
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* Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/interrupt.h>
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@ -33,6 +34,7 @@
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#define PCIE_CORE_CMD_STATUS_REG 0x4
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#define PCIE_CORE_DEV_REV_REG 0x8
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#define PCIE_CORE_PCIEXP_CAP 0xc0
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#define PCIE_CORE_PCIERR_CAP 0x100
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#define PCIE_CORE_ERR_CAPCTL_REG 0x118
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#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
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#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
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@ -857,14 +859,11 @@ advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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switch (reg) {
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case PCI_EXP_SLTCTL:
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*value = PCI_EXP_SLTSTA_PDS << 16;
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return PCI_BRIDGE_EMUL_HANDLED;
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/*
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* PCI_EXP_RTCTL and PCI_EXP_RTSTA are also supported, but do not need
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* to be handled here, because their values are stored in emulated
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* config space buffer, and we read them from there when needed.
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* PCI_EXP_SLTCAP, PCI_EXP_SLTCTL, PCI_EXP_RTCTL and PCI_EXP_RTSTA are
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* also supported, but do not need to be handled here, because their
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* values are stored in emulated config space buffer, and we read them
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* from there when needed.
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*/
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case PCI_EXP_LNKCAP: {
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@ -944,11 +943,89 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
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}
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}
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static pci_bridge_emul_read_status_t
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advk_pci_bridge_emul_ext_conf_read(struct pci_bridge_emul *bridge,
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int reg, u32 *value)
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{
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struct advk_pcie *pcie = bridge->data;
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switch (reg) {
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case 0:
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*value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg);
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/*
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* PCI_EXT_CAP_NEXT bits are set to offset 0x150, but Armada
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* 3700 Functional Specification does not document registers
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* at those addresses.
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*
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* Thus we clear PCI_EXT_CAP_NEXT bits to make Advanced Error
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* Reporting Capability header the last Extended Capability.
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* If we obtain documentation for those registers in the
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* future, this can be changed.
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*/
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*value &= 0x000fffff;
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return PCI_BRIDGE_EMUL_HANDLED;
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case PCI_ERR_UNCOR_STATUS:
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case PCI_ERR_UNCOR_MASK:
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case PCI_ERR_UNCOR_SEVER:
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case PCI_ERR_COR_STATUS:
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case PCI_ERR_COR_MASK:
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case PCI_ERR_CAP:
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case PCI_ERR_HEADER_LOG + 0:
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case PCI_ERR_HEADER_LOG + 4:
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case PCI_ERR_HEADER_LOG + 8:
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case PCI_ERR_HEADER_LOG + 12:
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case PCI_ERR_ROOT_COMMAND:
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case PCI_ERR_ROOT_STATUS:
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case PCI_ERR_ROOT_ERR_SRC:
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*value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg);
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return PCI_BRIDGE_EMUL_HANDLED;
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default:
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return PCI_BRIDGE_EMUL_NOT_HANDLED;
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}
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}
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static void
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advk_pci_bridge_emul_ext_conf_write(struct pci_bridge_emul *bridge,
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int reg, u32 old, u32 new, u32 mask)
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{
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struct advk_pcie *pcie = bridge->data;
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switch (reg) {
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/* These are W1C registers, so clear other bits */
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case PCI_ERR_UNCOR_STATUS:
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case PCI_ERR_COR_STATUS:
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case PCI_ERR_ROOT_STATUS:
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new &= mask;
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fallthrough;
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case PCI_ERR_UNCOR_MASK:
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case PCI_ERR_UNCOR_SEVER:
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case PCI_ERR_COR_MASK:
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case PCI_ERR_CAP:
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case PCI_ERR_HEADER_LOG + 0:
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case PCI_ERR_HEADER_LOG + 4:
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case PCI_ERR_HEADER_LOG + 8:
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case PCI_ERR_HEADER_LOG + 12:
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case PCI_ERR_ROOT_COMMAND:
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case PCI_ERR_ROOT_ERR_SRC:
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advk_writel(pcie, new, PCIE_CORE_PCIERR_CAP + reg);
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break;
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default:
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break;
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}
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}
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static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {
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.read_base = advk_pci_bridge_emul_base_conf_read,
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.write_base = advk_pci_bridge_emul_base_conf_write,
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.read_pcie = advk_pci_bridge_emul_pcie_conf_read,
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.write_pcie = advk_pci_bridge_emul_pcie_conf_write,
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.read_ext = advk_pci_bridge_emul_ext_conf_read,
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.write_ext = advk_pci_bridge_emul_ext_conf_write,
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};
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/*
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@ -977,8 +1054,25 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie)
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/* Support interrupt A for MSI feature */
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bridge->conf.intpin = PCI_INTERRUPT_INTA;
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/* Aardvark HW provides PCIe Capability structure in version 2 */
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bridge->pcie_conf.cap = cpu_to_le16(2);
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/*
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* Aardvark HW provides PCIe Capability structure in version 2 and
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* indicate slot support, which is emulated.
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*/
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bridge->pcie_conf.cap = cpu_to_le16(2 | PCI_EXP_FLAGS_SLOT);
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/*
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* Set Presence Detect State bit permanently since there is no support
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* for unplugging the card nor detecting whether it is plugged. (If a
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* platform exists in the future that supports it, via a GPIO for
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* example, it should be implemented via this bit.)
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*
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* Set physical slot number to 1 since there is only one port and zero
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* value is reserved for ports within the same silicon as Root Port
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* which is not our case.
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*/
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bridge->pcie_conf.slotcap = cpu_to_le32(FIELD_PREP(PCI_EXP_SLTCAP_PSN,
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1));
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bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS);
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/* Indicates supports for Completion Retry Status */
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bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS);
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