drm/amd/display: BIOS LTTPR Caps Interface
[WHY] Some platforms will have LTTPR capabilities forced on by VBIOS flags; the functions added here will access those flags. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -916,6 +916,143 @@ static enum bp_result bios_parser_get_soc_bb_info(
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return result;
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}
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static enum bp_result get_lttpr_caps_v4_1(
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struct bios_parser *bp,
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uint8_t *dce_caps)
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{
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enum bp_result result = BP_RESULT_OK;
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struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
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if (!dce_caps)
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return BP_RESULT_BADINPUT;
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if (!DATA_TABLES(dce_info))
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return BP_RESULT_BADBIOSTABLE;
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disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
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DATA_TABLES(dce_info));
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if (!disp_cntl_tbl)
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return BP_RESULT_BADBIOSTABLE;
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*dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
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return result;
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}
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static enum bp_result get_lttpr_caps_v4_2(
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struct bios_parser *bp,
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uint8_t *dce_caps)
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{
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enum bp_result result = BP_RESULT_OK;
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struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
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if (!dce_caps)
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return BP_RESULT_BADINPUT;
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if (!DATA_TABLES(dce_info))
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return BP_RESULT_BADBIOSTABLE;
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disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
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DATA_TABLES(dce_info));
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if (!disp_cntl_tbl)
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return BP_RESULT_BADBIOSTABLE;
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*dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
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return result;
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}
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static enum bp_result get_lttpr_caps_v4_3(
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struct bios_parser *bp,
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uint8_t *dce_caps)
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{
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enum bp_result result = BP_RESULT_OK;
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struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL;
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if (!dce_caps)
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return BP_RESULT_BADINPUT;
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if (!DATA_TABLES(dce_info))
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return BP_RESULT_BADBIOSTABLE;
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disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3,
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DATA_TABLES(dce_info));
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if (!disp_cntl_tbl)
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return BP_RESULT_BADBIOSTABLE;
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*dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
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return result;
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}
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static enum bp_result get_lttpr_caps_v4_4(
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struct bios_parser *bp,
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uint8_t *dce_caps)
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{
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enum bp_result result = BP_RESULT_OK;
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struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
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if (!dce_caps)
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return BP_RESULT_BADINPUT;
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if (!DATA_TABLES(dce_info))
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return BP_RESULT_BADBIOSTABLE;
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disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
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DATA_TABLES(dce_info));
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if (!disp_cntl_tbl)
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return BP_RESULT_BADBIOSTABLE;
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*dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
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return result;
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}
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static enum bp_result bios_parser_get_lttpr_caps(
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struct dc_bios *dcb,
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uint8_t *dce_caps)
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{
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struct bios_parser *bp = BP_FROM_DCB(dcb);
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enum bp_result result = BP_RESULT_UNSUPPORTED;
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struct atom_common_table_header *header;
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struct atom_data_revision tbl_revision;
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if (!DATA_TABLES(dce_info))
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return BP_RESULT_UNSUPPORTED;
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header = GET_IMAGE(struct atom_common_table_header,
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DATA_TABLES(dce_info));
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get_atom_data_table_revision(header, &tbl_revision);
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switch (tbl_revision.major) {
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case 4:
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switch (tbl_revision.minor) {
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case 1:
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result = get_lttpr_caps_v4_1(bp, dce_caps);
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break;
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case 2:
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result = get_lttpr_caps_v4_2(bp, dce_caps);
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break;
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case 3:
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result = get_lttpr_caps_v4_3(bp, dce_caps);
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break;
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case 4:
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result = get_lttpr_caps_v4_4(bp, dce_caps);
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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return result;
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}
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static enum bp_result get_embedded_panel_info_v2_1(
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struct bios_parser *bp,
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struct embedded_panel_info *info)
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@ -2531,6 +2668,8 @@ static const struct dc_vbios_funcs vbios_funcs = {
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.get_soc_bb_info = bios_parser_get_soc_bb_info,
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.get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info,
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.get_lttpr_caps = bios_parser_get_lttpr_caps,
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};
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static bool bios_parser2_construct(
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@ -150,6 +150,9 @@ struct dc_vbios_funcs {
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struct dc_bios *dcb,
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struct graphics_object_id object_id,
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struct bp_disp_connector_caps_info *info);
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enum bp_result (*get_lttpr_caps)(
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struct dc_bios *dcb,
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uint8_t *dce_caps);
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};
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struct bios_registers {
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@ -981,6 +981,40 @@ struct atom_display_controller_info_v4_2
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uint8_t reserved3[8];
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};
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struct atom_display_controller_info_v4_3
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{
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struct atom_common_table_header table_header;
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uint32_t display_caps;
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uint32_t bootup_dispclk_10khz;
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uint16_t dce_refclk_10khz;
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uint16_t i2c_engine_refclk_10khz;
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uint16_t dvi_ss_percentage; // in unit of 0.001%
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uint16_t dvi_ss_rate_10hz;
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uint16_t hdmi_ss_percentage; // in unit of 0.001%
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uint16_t hdmi_ss_rate_10hz;
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uint16_t dp_ss_percentage; // in unit of 0.001%
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uint16_t dp_ss_rate_10hz;
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uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
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uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
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uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
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uint8_t ss_reserved;
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uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
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uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
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uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
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uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
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uint16_t dpphy_refclk_10khz;
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uint16_t reserved2;
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uint8_t dcnip_min_ver;
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uint8_t dcnip_max_ver;
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uint8_t max_disp_pipe_num;
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uint8_t max_vbios_active_disp_pipe_num;
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uint8_t max_ppll_num;
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uint8_t max_disp_phy_num;
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uint8_t max_aux_pairs;
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uint8_t remotedisplayconfig;
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uint8_t reserved3[8];
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};
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struct atom_display_controller_info_v4_4 {
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struct atom_common_table_header table_header;
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uint32_t display_caps;
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@ -1043,7 +1077,8 @@ enum dce_info_caps_def
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DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04,
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// only for VBIOS
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DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08,
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// only for VBIOS
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DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE =0x20,
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};
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/*
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