arm64: dts: ti: k3-am654-base-board: Add DDR carveout memory nodes for R5Fs
The R5F processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. Four carveout reserved memory nodes have been added with two each (1 MB and 15 MB in size) used for each of the MCU R5F remote processor devices on all the TI K3 AM65x boards. These nodes are assigned to the respective rproc device nodes as well. The current carveout addresses and sizes are defined statically for each device. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. Note that the R5F1 carveouts are needed only if the corresponding R5F cluster is running in Split (non-LockStep) mode. The corresponding reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20201029033802.15366-4-s-anna@ti.com
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@ -29,11 +29,36 @@
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: secure-ddr@9e800000 {
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reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
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alignment = <0x1000>;
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no-map;
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};
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mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa0000000 0 0x100000>;
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no-map;
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};
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mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa0100000 0 0xf00000>;
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no-map;
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};
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mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa1000000 0 0x100000>;
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no-map;
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};
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mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa1100000 0 0xf00000>;
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no-map;
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};
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};
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gpio-keys {
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@ -442,10 +467,14 @@
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};
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&mcu_r5fss0_core0 {
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memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
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<&mcu_r5fss0_core0_memory_region>;
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mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
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};
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&mcu_r5fss0_core1 {
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memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
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<&mcu_r5fss0_core1_memory_region>;
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mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
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};
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