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- xgene : potential null pointer fix 

- omap : switch to spdx license and use of_device_get_match_data() to match data
 
 - ti-msgmgr : cleanup and optimisation. New TI specific feature - secure proxy thread.
 
 - mediatek : add driver for CMDQ controller.
 
 - nxp : add driver for MU controller
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Merge tag 'mailbox-v4.19' of git://git.linaro.org/landing-teams/working/fujitsu/integration

Pull mailbox updates from Jassi Brar:

 - xgene: potential null pointer fix

 - omap: switch to spdx license and use of_device_get_match_data() to
   match data

 - ti-msgmgr: cleanup and optimisation. New TI specific feature - secure
   proxy thread.

 - mediatek: add driver for CMDQ controller.

 - nxp: add driver for MU controller

* tag 'mailbox-v4.19' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: Add support for i.MX messaging unit
  dt-bindings: mailbox: imx-mu: add generic MU channel support
  dt-bindings: arm: fsl: add mu binding doc
  mailbox: add MODULE_LICENSE() for mtk-cmdq-mailbox.c
  mailbox: mediatek: Add Mediatek CMDQ driver
  dt-bindings: soc: Add documentation for the MediaTek GCE unit
  mailbox: ti-msgmgr: Add support for Secure Proxy
  dt-bindings: mailbox: Add support for secure proxy threads
  mailbox: ti-msgmgr: Move the memory region name to descriptor
  mailbox: ti-msgmgr: Change message count mask to be descriptor based
  mailbox: ti-msgmgr: Allocate Rx channel resources only on request
  mailbox: ti-msgmgr: Get rid of unused structure members
  mailbox/omap: use of_device_get_match_data() to get match data
  mailbox/omap: switch to SPDX license identifier
  mailbox: xgene-slimpro: Fix potential NULL pointer dereference
This commit is contained in:
Linus Torvalds 2018-08-16 10:16:08 -07:00
parent ea93102f32 2bb7005696
commit 9502f0d1d9
13 changed files with 1535 additions and 89 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
Documentation/devicetree/bindings/mailbox/fsl,mu.txt Normal file
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@ -0,0 +1,54 @@
NXP i.MX Messaging Unit (MU)
--------------------------------------------------------------------
The Messaging Unit module enables two processors within the SoC to
communicate and coordinate by passing messages (e.g. data, status
and control) through the MU interface. The MU also provides the ability
for one processor to signal the other processor using interrupts.
Because the MU manages the messaging between processors, the MU uses
different clocks (from each side of the different peripheral buses).
Therefore, the MU must synchronize the accesses from one side to the
other. The MU accomplishes synchronization using two sets of matching
registers (Processor A-facing, Processor B-facing).
Messaging Unit Device Node:
=============================
Required properties:
-------------------
- compatible : should be "fsl,<chip>-mu", the supported chips include
imx6sx, imx7s, imx8qxp, imx8qm.
The "fsl,imx6sx-mu" compatible is seen as generic and should
be included together with SoC specific compatible.
- reg : Should contain the registers location and length
- interrupts : Interrupt number. The interrupt specifier format depends
on the interrupt controller parent.
- #mbox-cells: Must be 2.
<&phandle type channel>
phandle : Label name of controller
type : Channel type
channel : Channel number
This MU support 4 type of unidirectional channels, each type
has 4 channels. A total of 16 channels. Following types are
supported:
0 - TX channel with 32bit transmit register and IRQ transmit
acknowledgment support.
1 - RX channel with 32bit receive register and IRQ support
2 - TX doorbell channel. Without own register and no ACK support.
3 - RX doorbell channel.
Optional properties:
-------------------
- clocks : phandle to the input clock.
- fsl,mu-side-b : Should be set for side B MU.
Examples:
--------
lsio_mu0: mailbox@5d1b0000 {
compatible = "fsl,imx8qxp-mu";
reg = <0x0 0x5d1b0000 0x0 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};

57
Documentation/devicetree/bindings/mailbox/mtk-gce.txt Normal file
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@ -0,0 +1,57 @@
MediaTek GCE
===============
The Global Command Engine (GCE) is used to help read/write registers with
critical time limitation, such as updating display configuration during the
vblank. The GCE can be used to implement the Command Queue (CMDQ) driver.
CMDQ driver uses mailbox framework for communication. Please refer to
mailbox.txt for generic information about mailbox device-tree bindings.
Required properties:
- compatible: Must be "mediatek,mt8173-gce"
- reg: Address range of the GCE unit
- interrupts: The interrupt signal from the GCE block
- clock: Clocks according to the common clock binding
- clock-names: Must be "gce" to stand for GCE clock
- #mbox-cells: Should be 3.
<&phandle channel priority atomic_exec>
phandle: Label name of a gce node.
channel: Channel of mailbox. Be equal to the thread id of GCE.
priority: Priority of GCE thread.
atomic_exec: GCE processing continuous packets of commands in atomic
way.
Required properties for a client device:
- mboxes: Client use mailbox to communicate with GCE, it should have this
property and list of phandle, mailbox specifiers.
- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding
to the register address.
Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as
sub-system ids, thread priority, event ids.
Example:
gce: gce@10212000 {
compatible = "mediatek,mt8173-gce";
reg = <0 0x10212000 0 0x1000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_GCE>;
clock-names = "gce";
thread-num = CMDQ_THR_MAX_COUNT;
#mbox-cells = <3>;
};
Example for a client device:
mmsys: clock-controller@14000000 {
compatible = "mediatek,mt8173-mmsys";
mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,
<&gce 1 CMDQ_THR_PRIO_LOWEST 1>;
mediatek,gce-subsys = <SUBSYS_1400XXXX>;
mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF
CMDQ_EVENT_MUTEX1_STREAM_EOF>;
...
};

50
Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt Normal file
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@ -0,0 +1,50 @@
Texas Instruments' Secure Proxy
========================================
The Texas Instruments' secure proxy is a mailbox controller that has
configurable queues selectable at SoC(System on Chip) integration. The
Message manager is broken up into different address regions that are
called "threads" or "proxies" - each instance is unidirectional and is
instantiated at SoC integration level by system controller to indicate
receive or transmit path.
Message Manager Device Node:
===========================
Required properties:
--------------------
- compatible: Shall be "ti,am654-secure-proxy"
- reg-names target_data - Map the proxy data region
rt - Map the realtime status region
scfg - Map the configuration region
- reg: Contains the register map per reg-names.
- #mbox-cells Shall be 1 and shall refer to the transfer path
called thread.
- interrupt-names: Contains interrupt names matching the rx transfer path
for a given SoC. Receive interrupts shall be of the
format: "rx_<PID>".
- interrupts: Contains the interrupt information corresponding to
interrupt-names property.
Example(AM654):
------------
secure_proxy: mailbox@32c00000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x0 0x32c00000 0x0 0x100000>,
<0x0 0x32400000 0x0 0x100000>,
<0x0 0x32800000 0x0 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
dmsc: dmsc {
[...]
mbox-names = "rx", "tx";
# RX Thread ID is 11
# TX Thread ID is 13
mboxes= <&secure_proxy 11>,
<&secure_proxy 13>;
[...]
};

16
drivers/mailbox/Kconfig
View File

@ -15,6 +15,12 @@ config ARM_MHU
The controller has 3 mailbox channels, the last of which can be
used in Secure mode only.
config IMX_MBOX
tristate "i.MX Mailbox"
depends on ARCH_MXC || COMPILE_TEST
help
Mailbox implementation for i.MX Messaging Unit (MU).
config PLATFORM_MHU
tristate "Platform MHU Mailbox"
depends on OF
@ -189,4 +195,14 @@ config STM32_IPCC
Mailbox implementation for STMicroelectonics STM32 family chips
with hardware for Inter-Processor Communication Controller (IPCC)
between processors. Say Y here if you want to have this support.
config MTK_CMDQ_MBOX
tristate "MediaTek CMDQ Mailbox Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
select MTK_INFRACFG
help
Say yes here to add support for the MediaTek Command Queue (CMDQ)
mailbox driver. The CMDQ is used to help read/write registers with
critical time limitation, such as updating display configuration
during the vblank.
endif

4
drivers/mailbox/Makefile
View File

@ -7,6 +7,8 @@ obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o
obj-$(CONFIG_ARM_MHU) += arm_mhu.o
obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o
obj-$(CONFIG_PLATFORM_MHU) += platform_mhu.o
obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o
@ -40,3 +42,5 @@ obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o

358
drivers/mailbox/imx-mailbox.c Normal file
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@ -0,0 +1,358 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
*/
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mailbox_controller.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/slab.h>
/* Transmit Register */
#define IMX_MU_xTRn(x) (0x00 + 4 * (x))
/* Receive Register */
#define IMX_MU_xRRn(x) (0x10 + 4 * (x))
/* Status Register */
#define IMX_MU_xSR 0x20
#define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
#define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
#define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
#define IMX_MU_xSR_BRDIP BIT(9)
/* Control Register */
#define IMX_MU_xCR 0x24
/* General Purpose Interrupt Enable */
#define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
/* Receive Interrupt Enable */
#define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
/* Transmit Interrupt Enable */
#define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
/* General Purpose Interrupt Request */
#define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
#define IMX_MU_CHANS 16
#define IMX_MU_CHAN_NAME_SIZE 20
enum imx_mu_chan_type {
IMX_MU_TYPE_TX, /* Tx */
IMX_MU_TYPE_RX, /* Rx */
IMX_MU_TYPE_TXDB, /* Tx doorbell */
IMX_MU_TYPE_RXDB, /* Rx doorbell */
};
struct imx_mu_con_priv {
unsigned int idx;
char irq_desc[IMX_MU_CHAN_NAME_SIZE];
enum imx_mu_chan_type type;
struct mbox_chan *chan;
struct tasklet_struct txdb_tasklet;
};
struct imx_mu_priv {
struct device *dev;
void __iomem *base;
spinlock_t xcr_lock; /* control register lock */
struct mbox_controller mbox;
struct mbox_chan mbox_chans[IMX_MU_CHANS];
struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
struct clk *clk;
int irq;
bool side_b;
};
static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
{
return container_of(mbox, struct imx_mu_priv, mbox);
}
static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
{
iowrite32(val, priv->base + offs);
}
static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
{
return ioread32(priv->base + offs);
}
static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&priv->xcr_lock, flags);
val = imx_mu_read(priv, IMX_MU_xCR);
val &= ~clr;
val |= set;
imx_mu_write(priv, val, IMX_MU_xCR);
spin_unlock_irqrestore(&priv->xcr_lock, flags);
return val;
}
static void imx_mu_txdb_tasklet(unsigned long data)
{
struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
mbox_chan_txdone(cp->chan, 0);
}
static irqreturn_t imx_mu_isr(int irq, void *p)
{
struct mbox_chan *chan = p;
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
struct imx_mu_con_priv *cp = chan->con_priv;
u32 val, ctrl, dat;
ctrl = imx_mu_read(priv, IMX_MU_xCR);
val = imx_mu_read(priv, IMX_MU_xSR);
switch (cp->type) {
case IMX_MU_TYPE_TX:
val &= IMX_MU_xSR_TEn(cp->idx) &
(ctrl & IMX_MU_xCR_TIEn(cp->idx));
break;
case IMX_MU_TYPE_RX:
val &= IMX_MU_xSR_RFn(cp->idx) &
(ctrl & IMX_MU_xCR_RIEn(cp->idx));
break;
case IMX_MU_TYPE_RXDB:
val &= IMX_MU_xSR_GIPn(cp->idx) &
(ctrl & IMX_MU_xCR_GIEn(cp->idx));
break;
default:
break;
}
if (!val)
return IRQ_NONE;
if (val == IMX_MU_xSR_TEn(cp->idx)) {
imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
mbox_chan_txdone(chan, 0);
} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx));
mbox_chan_received_data(chan, (void *)&dat);
} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), IMX_MU_xSR);
mbox_chan_received_data(chan, NULL);
} else {
dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static int imx_mu_send_data(struct mbox_chan *chan, void *data)
{
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
struct imx_mu_con_priv *cp = chan->con_priv;
u32 *arg = data;
switch (cp->type) {
case IMX_MU_TYPE_TX:
imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx));
imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
break;
case IMX_MU_TYPE_TXDB:
imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
tasklet_schedule(&cp->txdb_tasklet);
break;
default:
dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
return -EINVAL;
}
return 0;
}
static int imx_mu_startup(struct mbox_chan *chan)
{
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
struct imx_mu_con_priv *cp = chan->con_priv;
int ret;
if (cp->type == IMX_MU_TYPE_TXDB) {
/* Tx doorbell don't have ACK support */
tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
(unsigned long)cp);
return 0;
}
ret = request_irq(priv->irq, imx_mu_isr, IRQF_SHARED, cp->irq_desc,
chan);
if (ret) {
dev_err(priv->dev,
"Unable to acquire IRQ %d\n", priv->irq);
return ret;
}
switch (cp->type) {
case IMX_MU_TYPE_RX:
imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
break;
case IMX_MU_TYPE_RXDB:
imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
break;
default:
break;
}
return 0;
}
static void imx_mu_shutdown(struct mbox_chan *chan)
{
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
struct imx_mu_con_priv *cp = chan->con_priv;
if (cp->type == IMX_MU_TYPE_TXDB)
tasklet_kill(&cp->txdb_tasklet);
imx_mu_xcr_rmw(priv, 0,
IMX_MU_xCR_TIEn(cp->idx) | IMX_MU_xCR_RIEn(cp->idx));
free_irq(priv->irq, chan);
}
static const struct mbox_chan_ops imx_mu_ops = {
.send_data = imx_mu_send_data,
.startup = imx_mu_startup,
.shutdown = imx_mu_shutdown,
};
static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
const struct of_phandle_args *sp)
{
u32 type, idx, chan;
if (sp->args_count != 2) {
dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
return ERR_PTR(-EINVAL);
}
type = sp->args[0]; /* channel type */
idx = sp->args[1]; /* index */
chan = type * 4 + idx;
if (chan >= mbox->num_chans) {
dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
return ERR_PTR(-EINVAL);
}
return &mbox->chans[chan];
}
static void imx_mu_init_generic(struct imx_mu_priv *priv)
{
if (priv->side_b)
return;
/* Set default MU configuration */
imx_mu_write(priv, 0, IMX_MU_xCR);
}
static int imx_mu_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct resource *iomem;
struct imx_mu_priv *priv;
unsigned int i;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
priv->base = devm_ioremap_resource(&pdev->dev, iomem);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
priv->irq = platform_get_irq(pdev, 0);
if (priv->irq < 0)
return priv->irq;
priv->clk = devm_clk_get(dev, NULL);
if (IS_ERR(priv->clk)) {
if (PTR_ERR(priv->clk) != -ENOENT)
return PTR_ERR(priv->clk);
priv->clk = NULL;
}
ret = clk_prepare_enable(priv->clk);
if (ret) {
dev_err(dev, "Failed to enable clock\n");
return ret;
}
for (i = 0; i < IMX_MU_CHANS; i++) {
struct imx_mu_con_priv *cp = &priv->con_priv[i];
cp->idx = i % 4;
cp->type = i >> 2;
cp->chan = &priv->mbox_chans[i];
priv->mbox_chans[i].con_priv = cp;
snprintf(cp->irq_desc, sizeof(cp->irq_desc),
"imx_mu_chan[%i-%i]", cp->type, cp->idx);
}
priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
spin_lock_init(&priv->xcr_lock);
priv->mbox.dev = dev;
priv->mbox.ops = &imx_mu_ops;
priv->mbox.chans = priv->mbox_chans;
priv->mbox.num_chans = IMX_MU_CHANS;
priv->mbox.of_xlate = imx_mu_xlate;
priv->mbox.txdone_irq = true;
platform_set_drvdata(pdev, priv);
imx_mu_init_generic(priv);
return mbox_controller_register(&priv->mbox);
}
static int imx_mu_remove(struct platform_device *pdev)
{
struct imx_mu_priv *priv = platform_get_drvdata(pdev);
mbox_controller_unregister(&priv->mbox);
clk_disable_unprepare(priv->clk);
return 0;
}
static const struct of_device_id imx_mu_dt_ids[] = {
{ .compatible = "fsl,imx6sx-mu" },
{ },
};
MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
static struct platform_driver imx_mu_driver = {
.probe = imx_mu_probe,
.remove = imx_mu_remove,
.driver = {
.name = "imx_mu",
.of_match_table = imx_mu_dt_ids,
},
};
module_platform_driver(imx_mu_driver);
MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
MODULE_DESCRIPTION("Message Unit driver for i.MX");
MODULE_LICENSE("GPL v2");

6
drivers/mailbox/mailbox-xgene-slimpro.c
View File

@ -195,9 +195,9 @@ static int slimpro_mbox_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, ctx);
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mb_base = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
if (!mb_base)
return -ENOMEM;
mb_base = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(mb_base))
return PTR_ERR(mb_base);
/* Setup mailbox links */
for (i = 0; i < MBOX_CNT; i++) {

571
drivers/mailbox/mtk-cmdq-mailbox.c Normal file
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@ -0,0 +1,571 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mailbox_controller.h>
#include <linux/mailbox/mtk-cmdq-mailbox.h>
#include <linux/of_device.h>
#define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
#define CMDQ_IRQ_MASK 0xffff
#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
#define CMDQ_CURR_IRQ_STATUS 0x10
#define CMDQ_THR_SLOT_CYCLES 0x30
#define CMDQ_THR_BASE 0x100
#define CMDQ_THR_SIZE 0x80
#define CMDQ_THR_WARM_RESET 0x00
#define CMDQ_THR_ENABLE_TASK 0x04
#define CMDQ_THR_SUSPEND_TASK 0x08
#define CMDQ_THR_CURR_STATUS 0x0c
#define CMDQ_THR_IRQ_STATUS 0x10
#define CMDQ_THR_IRQ_ENABLE 0x14
#define CMDQ_THR_CURR_ADDR 0x20
#define CMDQ_THR_END_ADDR 0x24
#define CMDQ_THR_WAIT_TOKEN 0x30
#define CMDQ_THR_PRIORITY 0x40
#define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
#define CMDQ_THR_ENABLED 0x1
#define CMDQ_THR_DISABLED 0x0
#define CMDQ_THR_SUSPEND 0x1
#define CMDQ_THR_RESUME 0x0
#define CMDQ_THR_STATUS_SUSPENDED BIT(1)
#define CMDQ_THR_DO_WARM_RESET BIT(0)
#define CMDQ_THR_IRQ_DONE 0x1
#define CMDQ_THR_IRQ_ERROR 0x12
#define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE)
#define CMDQ_THR_IS_WAITING BIT(31)
#define CMDQ_JUMP_BY_OFFSET 0x10000000
#define CMDQ_JUMP_BY_PA 0x10000001
struct cmdq_thread {
struct mbox_chan *chan;
void __iomem *base;
struct list_head task_busy_list;
u32 priority;
bool atomic_exec;
};
struct cmdq_task {
struct cmdq *cmdq;
struct list_head list_entry;
dma_addr_t pa_base;
struct cmdq_thread *thread;
struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
};
struct cmdq {
struct mbox_controller mbox;
void __iomem *base;
u32 irq;
u32 thread_nr;
struct cmdq_thread *thread;
struct clk *clock;
bool suspended;
};
static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
{
u32 status;
writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);
/* If already disabled, treat as suspended successful. */
if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
return 0;
if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS,
status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) {
dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n",
(u32)(thread->base - cmdq->base));
return -EFAULT;
}
return 0;
}
static void cmdq_thread_resume(struct cmdq_thread *thread)
{
writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
}
static void cmdq_init(struct cmdq *cmdq)
{
WARN_ON(clk_enable(cmdq->clock) < 0);
writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
clk_disable(cmdq->clock);
}
static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
{
u32 warm_reset;
writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET,
warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET),
0, 10)) {
dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n",
(u32)(thread->base - cmdq->base));
return -EFAULT;
}
return 0;
}
static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread)
{
cmdq_thread_reset(cmdq, thread);
writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
}
/* notify GCE to re-fetch commands by setting GCE thread PC */
static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread)
{
writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
thread->base + CMDQ_THR_CURR_ADDR);
}
static void cmdq_task_insert_into_thread(struct cmdq_task *task)
{
struct device *dev = task->cmdq->mbox.dev;
struct cmdq_thread *thread = task->thread;
struct cmdq_task *prev_task = list_last_entry(
&thread->task_busy_list, typeof(*task), list_entry);
u64 *prev_task_base = prev_task->pkt->va_base;
/* let previous task jump to this task */
dma_sync_single_for_cpu(dev, prev_task->pa_base,
prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
(u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base;
dma_sync_single_for_device(dev, prev_task->pa_base,
prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
cmdq_thread_invalidate_fetched_data(thread);
}
static bool cmdq_command_is_wfe(u64 cmd)
{
u64 wfe_option = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
u64 wfe_op = (u64)(CMDQ_CODE_WFE << CMDQ_OP_CODE_SHIFT) << 32;
u64 wfe_mask = (u64)CMDQ_OP_CODE_MASK << 32 | 0xffffffff;
return ((cmd & wfe_mask) == (wfe_op | wfe_option));
}
/* we assume tasks in the same display GCE thread are waiting the same event. */
static void cmdq_task_remove_wfe(struct cmdq_task *task)
{
struct device *dev = task->cmdq->mbox.dev;
u64 *base = task->pkt->va_base;
int i;
dma_sync_single_for_cpu(dev, task->pa_base, task->pkt->cmd_buf_size,
DMA_TO_DEVICE);
for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
if (cmdq_command_is_wfe(base[i]))
base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
CMDQ_JUMP_PASS;
dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
DMA_TO_DEVICE);
}
static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
{
return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
}
static void cmdq_thread_wait_end(struct cmdq_thread *thread,
unsigned long end_pa)
{
struct device *dev = thread->chan->mbox->dev;
unsigned long curr_pa;
if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_ADDR,
curr_pa, curr_pa == end_pa, 1, 20))
dev_err(dev, "GCE thread cannot run to end.\n");
}
static void cmdq_task_exec_done(struct cmdq_task *task, enum cmdq_cb_status sta)
{
struct cmdq_task_cb *cb = &task->pkt->async_cb;
struct cmdq_cb_data data;
WARN_ON(cb->cb == (cmdq_async_flush_cb)NULL);
data.sta = sta;
data.data = cb->data;
cb->cb(data);
list_del(&task->list_entry);
}
static void cmdq_task_handle_error(struct cmdq_task *task)
{
struct cmdq_thread *thread = task->thread;
struct cmdq_task *next_task;
dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task);
WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0);
next_task = list_first_entry_or_null(&thread->task_busy_list,
struct cmdq_task, list_entry);
if (next_task)
writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
cmdq_thread_resume(thread);
}
static void cmdq_thread_irq_handler(struct cmdq *cmdq,
struct cmdq_thread *thread)
{
struct cmdq_task *task, *tmp, *curr_task = NULL;
u32 curr_pa, irq_flag, task_end_pa;
bool err;
irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);
/*
* When ISR call this function, another CPU core could run
* "release task" right before we acquire the spin lock, and thus
* reset / disable this GCE thread, so we need to check the enable
* bit of this GCE thread.
*/
if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
return;
if (irq_flag & CMDQ_THR_IRQ_ERROR)
err = true;
else if (irq_flag & CMDQ_THR_IRQ_DONE)
err = false;
else
return;
curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
list_entry) {
task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
if (curr_pa >= task->pa_base && curr_pa < task_end_pa)
curr_task = task;
if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) {
cmdq_task_exec_done(task, CMDQ_CB_NORMAL);
kfree(task);
} else if (err) {
cmdq_task_exec_done(task, CMDQ_CB_ERROR);
cmdq_task_handle_error(curr_task);
kfree(task);
}
if (curr_task)
break;
}
if (list_empty(&thread->task_busy_list)) {
cmdq_thread_disable(cmdq, thread);
clk_disable(cmdq->clock);
}
}
static irqreturn_t cmdq_irq_handler(int irq, void *dev)
{
struct cmdq *cmdq = dev;
unsigned long irq_status, flags = 0L;
int bit;
irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & CMDQ_IRQ_MASK;
if (!(irq_status ^ CMDQ_IRQ_MASK))
return IRQ_NONE;
for_each_clear_bit(bit, &irq_status, fls(CMDQ_IRQ_MASK)) {
struct cmdq_thread *thread = &cmdq->thread[bit];
spin_lock_irqsave(&thread->chan->lock, flags);
cmdq_thread_irq_handler(cmdq, thread);
spin_unlock_irqrestore(&thread->chan->lock, flags);
}
return IRQ_HANDLED;
}
static int cmdq_suspend(struct device *dev)
{
struct cmdq *cmdq = dev_get_drvdata(dev);
struct cmdq_thread *thread;
int i;
bool task_running = false;
cmdq->suspended = true;
for (i = 0; i < cmdq->thread_nr; i++) {
thread = &cmdq->thread[i];
if (!list_empty(&thread->task_busy_list)) {
task_running = true;
break;
}
}
if (task_running)
dev_warn(dev, "exist running task(s) in suspend\n");
clk_unprepare(cmdq->clock);
return 0;
}
static int cmdq_resume(struct device *dev)
{
struct cmdq *cmdq = dev_get_drvdata(dev);
WARN_ON(clk_prepare(cmdq->clock) < 0);
cmdq->suspended = false;
return 0;
}
static int cmdq_remove(struct platform_device *pdev)
{
struct cmdq *cmdq = platform_get_drvdata(pdev);
mbox_controller_unregister(&cmdq->mbox);
clk_unprepare(cmdq->clock);
if (cmdq->mbox.chans)
devm_kfree(&pdev->dev, cmdq->mbox.chans);
if (cmdq->thread)
devm_kfree(&pdev->dev, cmdq->thread);
devm_kfree(&pdev->dev, cmdq);
return 0;
}
static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
{
struct cmdq_pkt *pkt = (struct cmdq_pkt *)data;
struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
struct cmdq_task *task;
unsigned long curr_pa, end_pa;
/* Client should not flush new tasks if suspended. */
WARN_ON(cmdq->suspended);
task = kzalloc(sizeof(*task), GFP_ATOMIC);
task->cmdq = cmdq;
INIT_LIST_HEAD(&task->list_entry);
task->pa_base = pkt->pa_base;
task->thread = thread;
task->pkt = pkt;
if (list_empty(&thread->task_busy_list)) {
WARN_ON(clk_enable(cmdq->clock) < 0);
WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
writel(task->pa_base + pkt->cmd_buf_size,
thread->base + CMDQ_THR_END_ADDR);
writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
} else {
WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
end_pa = readl(thread->base + CMDQ_THR_END_ADDR);
/*
* Atomic execution should remove the following wfe, i.e. only
* wait event at first task, and prevent to pause when running.
*/
if (thread->atomic_exec) {
/* GCE is executing if command is not WFE */
if (!cmdq_thread_is_in_wfe(thread)) {
cmdq_thread_resume(thread);
cmdq_thread_wait_end(thread, end_pa);
WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
/* set to this task directly */
writel(task->pa_base,
thread->base + CMDQ_THR_CURR_ADDR);
} else {
cmdq_task_insert_into_thread(task);
cmdq_task_remove_wfe(task);
smp_mb(); /* modify jump before enable thread */
}
} else {
/* check boundary */
if (curr_pa == end_pa - CMDQ_INST_SIZE ||
curr_pa == end_pa) {
/* set to this task directly */
writel(task->pa_base,
thread->base + CMDQ_THR_CURR_ADDR);
} else {
cmdq_task_insert_into_thread(task);
smp_mb(); /* modify jump before enable thread */
}
}
writel(task->pa_base + pkt->cmd_buf_size,
thread->base + CMDQ_THR_END_ADDR);
cmdq_thread_resume(thread);
}
list_move_tail(&task->list_entry, &thread->task_busy_list);
return 0;
}
static int cmdq_mbox_startup(struct mbox_chan *chan)
{
return 0;
}
static void cmdq_mbox_shutdown(struct mbox_chan *chan)
{
}
static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
.send_data = cmdq_mbox_send_data,
.startup = cmdq_mbox_startup,
.shutdown = cmdq_mbox_shutdown,
};
static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox,
const struct of_phandle_args *sp)
{
int ind = sp->args[0];
struct cmdq_thread *thread;
if (ind >= mbox->num_chans)
return ERR_PTR(-EINVAL);
thread = (struct cmdq_thread *)mbox->chans[ind].con_priv;
thread->priority = sp->args[1];
thread->atomic_exec = (sp->args[2] != 0);
thread->chan = &mbox->chans[ind];
return &mbox->chans[ind];
}
static int cmdq_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct resource *res;
struct cmdq *cmdq;
int err, i;
cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
if (!cmdq)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
cmdq->base = devm_ioremap_resource(dev, res);
if (IS_ERR(cmdq->base)) {
dev_err(dev, "failed to ioremap gce\n");
return PTR_ERR(cmdq->base);
}
cmdq->irq = platform_get_irq(pdev, 0);
if (!cmdq->irq) {
dev_err(dev, "failed to get irq\n");
return -EINVAL;
}
err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
"mtk_cmdq", cmdq);
if (err < 0) {
dev_err(dev, "failed to register ISR (%d)\n", err);
return err;
}
dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
dev, cmdq->base, cmdq->irq);
cmdq->clock = devm_clk_get(dev, "gce");
if (IS_ERR(cmdq->clock)) {
dev_err(dev, "failed to get gce clk\n");
return PTR_ERR(cmdq->clock);
}
cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
cmdq->mbox.dev = dev;
cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
sizeof(*cmdq->mbox.chans), GFP_KERNEL);
if (!cmdq->mbox.chans)
return -ENOMEM;
cmdq->mbox.num_chans = cmdq->thread_nr;
cmdq->mbox.ops = &cmdq_mbox_chan_ops;
cmdq->mbox.of_xlate = cmdq_xlate;
/* make use of TXDONE_BY_ACK */
cmdq->mbox.txdone_irq = false;
cmdq->mbox.txdone_poll = false;
cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr,
sizeof(*cmdq->thread), GFP_KERNEL);
if (!cmdq->thread)
return -ENOMEM;
for (i = 0; i < cmdq->thread_nr; i++) {
cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
CMDQ_THR_SIZE * i;
INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i];
}
err = mbox_controller_register(&cmdq->mbox);
if (err < 0) {
dev_err(dev, "failed to register mailbox: %d\n", err);
return err;
}
platform_set_drvdata(pdev, cmdq);
WARN_ON(clk_prepare(cmdq->clock) < 0);
cmdq_init(cmdq);
return 0;
}
static const struct dev_pm_ops cmdq_pm_ops = {
.suspend = cmdq_suspend,
.resume = cmdq_resume,
};
static const struct of_device_id cmdq_of_ids[] = {
{.compatible = "mediatek,mt8173-gce", .data = (void *)16},
{}
};
static struct platform_driver cmdq_drv = {
.probe = cmdq_probe,
.remove = cmdq_remove,
.driver = {
.name = "mtk_cmdq",
.pm = &cmdq_pm_ops,
.of_match_table = cmdq_of_ids,
}
};
static int __init cmdq_drv_init(void)
{
return platform_driver_register(&cmdq_drv);
}
static void __exit cmdq_drv_exit(void)
{
platform_driver_unregister(&cmdq_drv);
}
subsys_initcall(cmdq_drv_init);
module_exit(cmdq_drv_exit);
MODULE_LICENSE("GPL v2");

31
drivers/mailbox/omap-mailbox.c
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
/*
* OMAP mailbox driver
*
@ -6,15 +7,6 @@
*
* Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
* Suman Anna <s-anna@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#include <linux/interrupt.h>
@ -77,6 +69,10 @@ struct omap_mbox_queue {
bool full;
};
struct omap_mbox_match_data {
u32 intr_type;
};
struct omap_mbox_device {
struct device *dev;
struct mutex cfg_lock;
@ -646,18 +642,21 @@ static const struct dev_pm_ops omap_mbox_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(omap_mbox_suspend, omap_mbox_resume)
};
static const struct omap_mbox_match_data omap2_data = { MBOX_INTR_CFG_TYPE1 };
static const struct omap_mbox_match_data omap4_data = { MBOX_INTR_CFG_TYPE2 };
static const struct of_device_id omap_mailbox_of_match[] = {
{
.compatible = "ti,omap2-mailbox",
.data = (void *)MBOX_INTR_CFG_TYPE1,
.data = &omap2_data,
},
{
.compatible = "ti,omap3-mailbox",
.data = (void *)MBOX_INTR_CFG_TYPE1,
.data = &omap2_data,
},
{
.compatible = "ti,omap4-mailbox",
.data = (void *)MBOX_INTR_CFG_TYPE2,
.data = &omap4_data,
},
{
/* end */
@ -700,7 +699,7 @@ static int omap_mbox_probe(struct platform_device *pdev)
struct omap_mbox_fifo *fifo;
struct device_node *node = pdev->dev.of_node;
struct device_node *child;
const struct of_device_id *match;
const struct omap_mbox_match_data *match_data;
u32 intr_type, info_count;
u32 num_users, num_fifos;
u32 tmp[3];
@ -712,10 +711,10 @@ static int omap_mbox_probe(struct platform_device *pdev)
return -ENODEV;
}
match = of_match_device(omap_mailbox_of_match, &pdev->dev);
if (!match)
match_data = of_device_get_match_data(&pdev->dev);
if (!match_data)
return -ENODEV;
intr_type = (u32)match->data;
intr_type = match_data->intr_type;
if (of_property_read_u32(node, "ti,mbox-num-users", &num_users))
return -ENODEV;

335
drivers/mailbox/ti-msgmgr.c
View File

@ -25,6 +25,17 @@
#define Q_STATE_OFFSET(queue) ((queue) * 0x4)
#define Q_STATE_ENTRY_COUNT_MASK (0xFFF000)
#define SPROXY_THREAD_OFFSET(tid) (0x1000 * (tid))
#define SPROXY_THREAD_DATA_OFFSET(tid, reg) \
(SPROXY_THREAD_OFFSET(tid) + ((reg) * 0x4) + 0x4)
#define SPROXY_THREAD_STATUS_OFFSET(tid) (SPROXY_THREAD_OFFSET(tid))
#define SPROXY_THREAD_STATUS_COUNT_MASK (0xFF)
#define SPROXY_THREAD_CTRL_OFFSET(tid) (0x1000 + SPROXY_THREAD_OFFSET(tid))
#define SPROXY_THREAD_CTRL_DIR_MASK (0x1 << 31)
/**
* struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor
* @queue_id: Queue Number for this path
@ -42,14 +53,18 @@ struct ti_msgmgr_valid_queue_desc {
* @queue_count: Number of Queues
* @max_message_size: Message size in bytes
* @max_messages: Number of messages
* @q_slices: Number of queue engines
* @q_proxies: Number of queue proxies per page
* @data_first_reg: First data register for proxy data region
* @data_last_reg: Last data register for proxy data region
* @status_cnt_mask: Mask for getting the status value
* @status_err_mask: Mask for getting the error value, if applicable
* @tx_polled: Do I need to use polled mechanism for tx
* @tx_poll_timeout_ms: Timeout in ms if polled
* @valid_queues: List of Valid queues that the processor can access
* @data_region_name: Name of the proxy data region
* @status_region_name: Name of the proxy status region
* @ctrl_region_name: Name of the proxy control region
* @num_valid_queues: Number of valid queues
* @is_sproxy: Is this an Secure Proxy instance?
*
* This structure is used in of match data to describe how integration
* for a specific compatible SoC is done.
@ -58,14 +73,18 @@ struct ti_msgmgr_desc {
u8 queue_count;
u8 max_message_size;
u8 max_messages;
u8 q_slices;
u8 q_proxies;
u8 data_first_reg;
u8 data_last_reg;
u32 status_cnt_mask;
u32 status_err_mask;
bool tx_polled;
int tx_poll_timeout_ms;
const struct ti_msgmgr_valid_queue_desc *valid_queues;
const char *data_region_name;
const char *status_region_name;
const char *ctrl_region_name;
int num_valid_queues;
bool is_sproxy;
};
/**
@ -78,6 +97,7 @@ struct ti_msgmgr_desc {
* @queue_buff_start: First register of Data Buffer
* @queue_buff_end: Last (or confirmation) register of Data buffer
* @queue_state: Queue status register
* @queue_ctrl: Queue Control register
* @chan: Mailbox channel
* @rx_buff: Receive buffer pointer allocated at probe, max_message_size
*/
@ -90,6 +110,7 @@ struct ti_queue_inst {
void __iomem *queue_buff_start;
void __iomem *queue_buff_end;
void __iomem *queue_state;
void __iomem *queue_ctrl;
struct mbox_chan *chan;
u32 *rx_buff;
};
@ -100,6 +121,7 @@ struct ti_queue_inst {
* @desc: Description of the SoC integration
* @queue_proxy_region: Queue proxy region where queue buffers are located
* @queue_state_debug_region: Queue status register regions
* @queue_ctrl_region: Queue Control register regions
* @num_valid_queues: Number of valid queues defined for the processor
* Note: other queues are probably reserved for other processors
* in the SoC.
@ -112,6 +134,7 @@ struct ti_msgmgr_inst {
const struct ti_msgmgr_desc *desc;
void __iomem *queue_proxy_region;
void __iomem *queue_state_debug_region;
void __iomem *queue_ctrl_region;
u8 num_valid_queues;
struct ti_queue_inst *qinsts;
struct mbox_controller mbox;
@ -120,24 +143,53 @@ struct ti_msgmgr_inst {
/**
* ti_msgmgr_queue_get_num_messages() - Get the number of pending messages
* @d: Description of message manager
* @qinst: Queue instance for which we check the number of pending messages
*
* Return: number of messages pending in the queue (0 == no pending messages)
*/
static inline int ti_msgmgr_queue_get_num_messages(struct ti_queue_inst *qinst)
static inline int
ti_msgmgr_queue_get_num_messages(const struct ti_msgmgr_desc *d,
struct ti_queue_inst *qinst)
{
u32 val;
u32 status_cnt_mask = d->status_cnt_mask;
/*
* We cannot use relaxed operation here - update may happen
* real-time.
*/
val = readl(qinst->queue_state) & Q_STATE_ENTRY_COUNT_MASK;
val >>= __ffs(Q_STATE_ENTRY_COUNT_MASK);
val = readl(qinst->queue_state) & status_cnt_mask;
val >>= __ffs(status_cnt_mask);
return val;
}
/**
* ti_msgmgr_queue_is_error() - Check to see if there is queue error
* @d: Description of message manager
* @qinst: Queue instance for which we check the number of pending messages
*
* Return: true if error, else false
*/
static inline bool ti_msgmgr_queue_is_error(const struct ti_msgmgr_desc *d,
struct ti_queue_inst *qinst)
{
u32 val;
/* Msgmgr has no error detection */
if (!d->is_sproxy)
return false;
/*
* We cannot use relaxed operation here - update may happen
* real-time.
*/
val = readl(qinst->queue_state) & d->status_err_mask;
return val ? true : false;
}
/**
* ti_msgmgr_queue_rx_interrupt() - Interrupt handler for receive Queue
* @irq: Interrupt number
@ -171,8 +223,14 @@ static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p)
return IRQ_NONE;
}
desc = inst->desc;
if (ti_msgmgr_queue_is_error(desc, qinst)) {
dev_err(dev, "Error on Rx channel %s\n", qinst->name);
return IRQ_NONE;
}
/* Do I actually have messages to read? */
msg_count = ti_msgmgr_queue_get_num_messages(qinst);
msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst);
if (!msg_count) {
/* Shared IRQ? */
dev_dbg(dev, "Spurious event - 0 pending data!\n");
@ -185,7 +243,6 @@ static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p)
* of how many bytes I should be reading. Let the client figure this
* out.. I just read the full message and pass it on..
*/
desc = inst->desc;
message.len = desc->max_message_size;
message.buf = (u8 *)qinst->rx_buff;
@ -228,12 +285,20 @@ static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p)
static bool ti_msgmgr_queue_peek_data(struct mbox_chan *chan)
{
struct ti_queue_inst *qinst = chan->con_priv;
struct device *dev = chan->mbox->dev;
struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
const struct ti_msgmgr_desc *desc = inst->desc;
int msg_count;
if (qinst->is_tx)
return false;
msg_count = ti_msgmgr_queue_get_num_messages(qinst);
if (ti_msgmgr_queue_is_error(desc, qinst)) {
dev_err(dev, "Error on channel %s\n", qinst->name);
return false;
}
msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst);
return msg_count ? true : false;
}
@ -247,12 +312,25 @@ static bool ti_msgmgr_queue_peek_data(struct mbox_chan *chan)
static bool ti_msgmgr_last_tx_done(struct mbox_chan *chan)
{
struct ti_queue_inst *qinst = chan->con_priv;
struct device *dev = chan->mbox->dev;
struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
const struct ti_msgmgr_desc *desc = inst->desc;
int msg_count;
if (!qinst->is_tx)
return false;
msg_count = ti_msgmgr_queue_get_num_messages(qinst);
if (ti_msgmgr_queue_is_error(desc, qinst)) {
dev_err(dev, "Error on channel %s\n", qinst->name);
return false;
}
msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst);
if (desc->is_sproxy) {
/* In secure proxy, msg_count indicates how many we can send */
return msg_count ? true : false;
}
/* if we have any messages pending.. */
return msg_count ? false : true;
@ -282,6 +360,11 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data)
}
desc = inst->desc;
if (ti_msgmgr_queue_is_error(desc, qinst)) {
dev_err(dev, "Error on channel %s\n", qinst->name);
return false;
}
if (desc->max_message_size < message->len) {
dev_err(dev, "Queue %s message length %zu > max %d\n",
qinst->name, message->len, desc->max_message_size);
@ -314,6 +397,53 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data)
return 0;
}
/**
* ti_msgmgr_queue_rx_irq_req() - RX IRQ request
* @dev: device pointer
* @d: descriptor for ti_msgmgr
* @qinst: Queue instance
* @chan: Channel pointer
*/
static int ti_msgmgr_queue_rx_irq_req(struct device *dev,
const struct ti_msgmgr_desc *d,
struct ti_queue_inst *qinst,
struct mbox_chan *chan)
{
int ret = 0;
char of_rx_irq_name[7];
struct device_node *np;
snprintf(of_rx_irq_name, sizeof(of_rx_irq_name),
"rx_%03d", d->is_sproxy ? qinst->proxy_id : qinst->queue_id);
/* Get the IRQ if not found */
if (qinst->irq < 0) {
np = of_node_get(dev->of_node);
if (!np)
return -ENODATA;
qinst->irq = of_irq_get_byname(np, of_rx_irq_name);
of_node_put(np);
if (qinst->irq < 0) {
dev_err(dev,
"QID %d PID %d:No IRQ[%s]: %d\n",
qinst->queue_id, qinst->proxy_id,
of_rx_irq_name, qinst->irq);
return qinst->irq;
}
}
/* With the expectation that the IRQ might be shared in SoC */
ret = request_irq(qinst->irq, ti_msgmgr_queue_rx_interrupt,
IRQF_SHARED, qinst->name, chan);
if (ret) {
dev_err(dev, "Unable to get IRQ %d on %s(res=%d)\n",
qinst->irq, qinst->name, ret);
}
return ret;
}
/**
* ti_msgmgr_queue_startup() - Startup queue
* @chan: Channel pointer
@ -322,19 +452,39 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data)
*/
static int ti_msgmgr_queue_startup(struct mbox_chan *chan)
{
struct ti_queue_inst *qinst = chan->con_priv;
struct device *dev = chan->mbox->dev;
struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
struct ti_queue_inst *qinst = chan->con_priv;
const struct ti_msgmgr_desc *d = inst->desc;
int ret;
int msg_count;
/*
* If sproxy is starting and can send messages, we are a Tx thread,
* else Rx
*/
if (d->is_sproxy) {
qinst->is_tx = (readl(qinst->queue_ctrl) &
SPROXY_THREAD_CTRL_DIR_MASK) ? false : true;
msg_count = ti_msgmgr_queue_get_num_messages(d, qinst);
if (!msg_count && qinst->is_tx) {
dev_err(dev, "%s: Cannot transmit with 0 credits!\n",
qinst->name);
return -EINVAL;
}
}
if (!qinst->is_tx) {
/*
* With the expectation that the IRQ might be shared in SoC
*/
ret = request_irq(qinst->irq, ti_msgmgr_queue_rx_interrupt,
IRQF_SHARED, qinst->name, chan);
/* Allocate usage buffer for rx */
qinst->rx_buff = kzalloc(d->max_message_size, GFP_KERNEL);
if (!qinst->rx_buff)
return -ENOMEM;
/* Request IRQ */
ret = ti_msgmgr_queue_rx_irq_req(dev, d, qinst, chan);
if (ret) {
dev_err(dev, "Unable to get IRQ %d on %s(res=%d)\n",
qinst->irq, qinst->name, ret);
kfree(qinst->rx_buff);
return ret;
}
}
@ -350,8 +500,10 @@ static void ti_msgmgr_queue_shutdown(struct mbox_chan *chan)
{
struct ti_queue_inst *qinst = chan->con_priv;
if (!qinst->is_tx)
if (!qinst->is_tx) {
free_irq(qinst->irq, chan);
kfree(qinst->rx_buff);
}
}
/**
@ -368,20 +520,38 @@ static struct mbox_chan *ti_msgmgr_of_xlate(struct mbox_controller *mbox,
struct ti_msgmgr_inst *inst;
int req_qid, req_pid;
struct ti_queue_inst *qinst;
int i;
const struct ti_msgmgr_desc *d;
int i, ncells;
inst = container_of(mbox, struct ti_msgmgr_inst, mbox);
if (WARN_ON(!inst))
return ERR_PTR(-EINVAL);
/* #mbox-cells is 2 */
if (p->args_count != 2) {
dev_err(inst->dev, "Invalid arguments in dt[%d] instead of 2\n",
p->args_count);
d = inst->desc;
if (d->is_sproxy)
ncells = 1;
else
ncells = 2;
if (p->args_count != ncells) {
dev_err(inst->dev, "Invalid arguments in dt[%d]. Must be %d\n",
p->args_count, ncells);
return ERR_PTR(-EINVAL);
}
if (ncells == 1) {
req_qid = 0;
req_pid = p->args[0];
} else {
req_qid = p->args[0];
req_pid = p->args[1];
}
if (d->is_sproxy) {
if (req_pid > d->num_valid_queues)
goto err;
qinst = &inst->qinsts[req_pid];
return qinst->chan;
}
for (qinst = inst->qinsts, i = 0; i < inst->num_valid_queues;
i++, qinst++) {
@ -389,6 +559,7 @@ static struct mbox_chan *ti_msgmgr_of_xlate(struct mbox_controller *mbox,
return qinst->chan;
}
err:
dev_err(inst->dev, "Queue ID %d, Proxy ID %d is wrong on %s\n",
req_qid, req_pid, p->np->name);
return ERR_PTR(-ENOENT);
@ -415,6 +586,8 @@ static int ti_msgmgr_queue_setup(int idx, struct device *dev,
struct ti_queue_inst *qinst,
struct mbox_chan *chan)
{
char *dir;
qinst->proxy_id = qd->proxy_id;
qinst->queue_id = qd->queue_id;
@ -424,40 +597,43 @@ static int ti_msgmgr_queue_setup(int idx, struct device *dev,
return -ERANGE;
}
qinst->is_tx = qd->is_tx;
snprintf(qinst->name, sizeof(qinst->name), "%s %s_%03d_%03d",
dev_name(dev), qinst->is_tx ? "tx" : "rx", qinst->queue_id,
qinst->proxy_id);
if (!qinst->is_tx) {
char of_rx_irq_name[7];
snprintf(of_rx_irq_name, sizeof(of_rx_irq_name),
"rx_%03d", qinst->queue_id);
qinst->irq = of_irq_get_byname(np, of_rx_irq_name);
if (qinst->irq < 0) {
dev_crit(dev,
"[%d]QID %d PID %d:No IRQ[%s]: %d\n",
idx, qinst->queue_id, qinst->proxy_id,
of_rx_irq_name, qinst->irq);
return qinst->irq;
}
/* Allocate usage buffer for rx */
qinst->rx_buff = devm_kzalloc(dev,
d->max_message_size, GFP_KERNEL);
if (!qinst->rx_buff)
return -ENOMEM;
}
if (d->is_sproxy) {
qinst->queue_buff_start = inst->queue_proxy_region +
Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, d->data_first_reg);
SPROXY_THREAD_DATA_OFFSET(qinst->proxy_id,
d->data_first_reg);
qinst->queue_buff_end = inst->queue_proxy_region +
Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, d->data_last_reg);
SPROXY_THREAD_DATA_OFFSET(qinst->proxy_id,
d->data_last_reg);
qinst->queue_state = inst->queue_state_debug_region +
SPROXY_THREAD_STATUS_OFFSET(qinst->proxy_id);
qinst->queue_ctrl = inst->queue_ctrl_region +
SPROXY_THREAD_CTRL_OFFSET(qinst->proxy_id);
/* XXX: DONOT read registers here!.. Some may be unusable */
dir = "thr";
snprintf(qinst->name, sizeof(qinst->name), "%s %s_%03d",
dev_name(dev), dir, qinst->proxy_id);
} else {
qinst->queue_buff_start = inst->queue_proxy_region +
Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id,
d->data_first_reg);
qinst->queue_buff_end = inst->queue_proxy_region +
Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id,
d->data_last_reg);
qinst->queue_state =
inst->queue_state_debug_region +
Q_STATE_OFFSET(qinst->queue_id);
qinst->is_tx = qd->is_tx;
dir = qinst->is_tx ? "tx" : "rx";
snprintf(qinst->name, sizeof(qinst->name), "%s %s_%03d_%03d",
dev_name(dev), dir, qinst->queue_id, qinst->proxy_id);
}
qinst->chan = chan;
/* Setup an error value for IRQ - Lazy allocation */
qinst->irq = -EINVAL;
chan->con_priv = qinst;
dev_dbg(dev, "[%d] qidx=%d pidx=%d irq=%d q_s=%p q_e = %p\n",
@ -494,19 +670,37 @@ static const struct ti_msgmgr_desc k2g_desc = {
.queue_count = 64,
.max_message_size = 64,
.max_messages = 128,
.q_slices = 1,
.q_proxies = 1,
.data_region_name = "queue_proxy_region",
.status_region_name = "queue_state_debug_region",
.data_first_reg = 16,
.data_last_reg = 31,
.status_cnt_mask = Q_STATE_ENTRY_COUNT_MASK,
.tx_polled = false,
.valid_queues = k2g_valid_queues,
.num_valid_queues = ARRAY_SIZE(k2g_valid_queues),
.is_sproxy = false,
};
static const struct ti_msgmgr_desc am654_desc = {
.queue_count = 190,
.num_valid_queues = 190,
.max_message_size = 60,
.data_region_name = "target_data",
.status_region_name = "rt",
.ctrl_region_name = "scfg",
.data_first_reg = 0,
.data_last_reg = 14,
.status_cnt_mask = SPROXY_THREAD_STATUS_COUNT_MASK,
.tx_polled = false,
.is_sproxy = true,
};
static const struct of_device_id ti_msgmgr_of_match[] = {
{.compatible = "ti,k2g-message-manager", .data = &k2g_desc},
{.compatible = "ti,am654-secure-proxy", .data = &am654_desc},
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, ti_msgmgr_of_match);
static int ti_msgmgr_probe(struct platform_device *pdev)
@ -546,17 +740,25 @@ static int ti_msgmgr_probe(struct platform_device *pdev)
inst->desc = desc;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"queue_proxy_region");
desc->data_region_name);
inst->queue_proxy_region = devm_ioremap_resource(dev, res);
if (IS_ERR(inst->queue_proxy_region))
return PTR_ERR(inst->queue_proxy_region);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"queue_state_debug_region");
desc->status_region_name);
inst->queue_state_debug_region = devm_ioremap_resource(dev, res);
if (IS_ERR(inst->queue_state_debug_region))
return PTR_ERR(inst->queue_state_debug_region);
if (desc->is_sproxy) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
desc->ctrl_region_name);
inst->queue_ctrl_region = devm_ioremap_resource(dev, res);
if (IS_ERR(inst->queue_ctrl_region))
return PTR_ERR(inst->queue_ctrl_region);
}
dev_dbg(dev, "proxy region=%p, queue_state=%p\n",
inst->queue_proxy_region, inst->queue_state_debug_region);
@ -578,13 +780,30 @@ static int ti_msgmgr_probe(struct platform_device *pdev)
return -ENOMEM;
inst->chans = chans;
if (desc->is_sproxy) {
struct ti_msgmgr_valid_queue_desc sproxy_desc;
/* All proxies may be valid in Secure Proxy instance */
for (i = 0; i < queue_count; i++, qinst++, chans++) {
sproxy_desc.queue_id = 0;
sproxy_desc.proxy_id = i;
ret = ti_msgmgr_queue_setup(i, dev, np, inst,
desc, &sproxy_desc, qinst,
chans);
if (ret)
return ret;
}
} else {
/* Only Some proxies are valid in Message Manager */
for (i = 0, queue_desc = desc->valid_queues;
i < queue_count; i++, qinst++, chans++, queue_desc++) {
ret = ti_msgmgr_queue_setup(i, dev, np, inst,
desc, queue_desc, qinst, chans);
desc, queue_desc, qinst,
chans);
if (ret)
return ret;
}
}
mbox = &inst->mbox;
mbox->dev = dev;

44
include/dt-bindings/gce/mt8173-gce.h Normal file
View File

@ -0,0 +1,44 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Houlong Wei <houlong.wei@mediatek.com>
*
*/
#ifndef _DT_BINDINGS_GCE_MT8173_H
#define _DT_BINDINGS_GCE_MT8173_H
/* GCE HW thread priority */
#define CMDQ_THR_PRIO_LOWEST 0
#define CMDQ_THR_PRIO_HIGHEST 1
/* GCE SUBSYS */
#define SUBSYS_1400XXXX 1
#define SUBSYS_1401XXXX 2
#define SUBSYS_1402XXXX 3
/* GCE HW EVENT */
#define CMDQ_EVENT_DISP_OVL0_SOF 11
#define CMDQ_EVENT_DISP_OVL1_SOF 12
#define CMDQ_EVENT_DISP_RDMA0_SOF 13
#define CMDQ_EVENT_DISP_RDMA1_SOF 14
#define CMDQ_EVENT_DISP_RDMA2_SOF 15
#define CMDQ_EVENT_DISP_WDMA0_SOF 16
#define CMDQ_EVENT_DISP_WDMA1_SOF 17
#define CMDQ_EVENT_DISP_OVL0_EOF 39
#define CMDQ_EVENT_DISP_OVL1_EOF 40
#define CMDQ_EVENT_DISP_RDMA0_EOF 41
#define CMDQ_EVENT_DISP_RDMA1_EOF 42
#define CMDQ_EVENT_DISP_RDMA2_EOF 43
#define CMDQ_EVENT_DISP_WDMA0_EOF 44
#define CMDQ_EVENT_DISP_WDMA1_EOF 45
#define CMDQ_EVENT_MUTEX0_STREAM_EOF 53
#define CMDQ_EVENT_MUTEX1_STREAM_EOF 54
#define CMDQ_EVENT_MUTEX2_STREAM_EOF 55
#define CMDQ_EVENT_MUTEX3_STREAM_EOF 56
#define CMDQ_EVENT_MUTEX4_STREAM_EOF 57
#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 63
#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 64
#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 65
#endif

77
include/linux/mailbox/mtk-cmdq-mailbox.h Normal file
View File

@ -0,0 +1,77 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018 MediaTek Inc.
*
*/
#ifndef __MTK_CMDQ_MAILBOX_H__
#define __MTK_CMDQ_MAILBOX_H__
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>
#define CMDQ_INST_SIZE 8 /* instruction is 64-bit */
#define CMDQ_SUBSYS_SHIFT 16
#define CMDQ_OP_CODE_SHIFT 24
#define CMDQ_JUMP_PASS CMDQ_INST_SIZE
#define CMDQ_WFE_UPDATE BIT(31)
#define CMDQ_WFE_WAIT BIT(15)
#define CMDQ_WFE_WAIT_VALUE 0x1
/*
* CMDQ_CODE_MASK:
* set write mask
* format: op mask
* CMDQ_CODE_WRITE:
* write value into target register
* format: op subsys address value
* CMDQ_CODE_JUMP:
* jump by offset
* format: op offset
* CMDQ_CODE_WFE:
* wait for event and clear
* it is just clear if no wait
* format: [wait] op event update:1 to_wait:1 wait:1
* [clear] op event update:1 to_wait:0 wait:0
* CMDQ_CODE_EOC:
* end of command
* format: op irq_flag
*/
enum cmdq_code {
CMDQ_CODE_MASK = 0x02,
CMDQ_CODE_WRITE = 0x04,
CMDQ_CODE_JUMP = 0x10,
CMDQ_CODE_WFE = 0x20,
CMDQ_CODE_EOC = 0x40,
};
enum cmdq_cb_status {
CMDQ_CB_NORMAL = 0,
CMDQ_CB_ERROR
};
struct cmdq_cb_data {
enum cmdq_cb_status sta;
void *data;
};
typedef void (*cmdq_async_flush_cb)(struct cmdq_cb_data data);
struct cmdq_task_cb {
cmdq_async_flush_cb cb;
void *data;
};
struct cmdq_pkt {
void *va_base;
dma_addr_t pa_base;
size_t cmd_buf_size; /* command occupied size */
size_t buf_size; /* real buffer size */
struct cmdq_task_cb cb;
struct cmdq_task_cb async_cb;
void *cl;
};
#endif /* __MTK_CMDQ_MAILBOX_H__ */

5
include/linux/omap-mailbox.h
View File

@ -1,9 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* omap-mailbox: interprocessor communication module for OMAP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef OMAP_MAILBOX_H