sh: Fix up the SH-5 build with caches enabled.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
1ee4ab09f3
commit
94ecd224c9
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@ -14,18 +14,6 @@
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#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
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#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
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#define __icbi() \
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{ \
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unsigned long __addr; \
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__addr = 0xa8000000; \
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__asm__ __volatile__( \
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"icbi %0\n\t" \
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: /* no output */ \
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: "m" (__m(__addr))); \
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}
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#endif
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/*
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* A brief note on ctrl_barrier(), the control register write barrier.
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*
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@ -44,7 +32,7 @@
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#define mb() __asm__ __volatile__ ("synco": : :"memory")
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#define rmb() mb()
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#define wmb() __asm__ __volatile__ ("synco": : :"memory")
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#define ctrl_barrier() __icbi()
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#define ctrl_barrier() __icbi(0xa8000000)
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#define read_barrier_depends() do { } while(0)
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#else
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#define mb() __asm__ __volatile__ ("": : :"memory")
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@ -63,6 +63,16 @@ do { \
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#define __restore_dsp(tsk) do { } while (0)
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#endif
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#if defined(CONFIG_CPU_SH4A)
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#define __icbi(addr) __asm__ __volatile__ ( "icbi @%0\n\t" : : "r" (addr))
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#else
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#define __icbi(addr) mb()
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#endif
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#define __ocbp(addr) __asm__ __volatile__ ( "ocbp @%0\n\t" : : "r" (addr))
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#define __ocbi(addr) __asm__ __volatile__ ( "ocbi @%0\n\t" : : "r" (addr))
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#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb @%0\n\t" : : "r" (addr))
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struct task_struct *__switch_to(struct task_struct *prev,
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struct task_struct *next);
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@ -37,6 +37,11 @@ do { \
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#define jump_to_uncached() do { } while (0)
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#define back_to_cached() do { } while (0)
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#define __icbi(addr) __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
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#define __ocbp(addr) __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
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#define __ocbi(addr) __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))
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#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb %0, 0\n\t" : : "r" (addr))
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static inline reg_size_t register_align(void *val)
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{
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return (unsigned long long)(signed long long)(signed long)val;
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@ -30,14 +30,6 @@ extern int dump_fpu(struct pt_regs *, elf_fpregset_t *);
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EXPORT_SYMBOL(dump_fpu);
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EXPORT_SYMBOL(kernel_thread);
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#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU)
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EXPORT_SYMBOL(clear_user_page);
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#endif
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#ifndef CONFIG_CACHE_OFF
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EXPORT_SYMBOL(flush_dcache_page);
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#endif
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#ifdef CONFIG_VT
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EXPORT_SYMBOL(screen_info);
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#endif
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@ -25,29 +25,6 @@ extern void __weak sh4__flush_region_init(void);
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/* Wired TLB entry for the D-cache */
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static unsigned long long dtlb_cache_slot;
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void __init cpu_cache_init(void)
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{
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/* Reserve a slot for dcache colouring in the DTLB */
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dtlb_cache_slot = sh64_get_wired_dtlb_entry();
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sh4__flush_region_init();
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}
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void __init kmap_coherent_init(void)
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{
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/* XXX ... */
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}
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void *kmap_coherent(struct page *page, unsigned long addr)
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{
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/* XXX ... */
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return NULL;
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}
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void kunmap_coherent(void)
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{
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}
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#ifdef CONFIG_DCACHE_DISABLED
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#define sh64_dcache_purge_all() do { } while (0)
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#define sh64_dcache_purge_coloured_phy_page(paddr, eaddr) do { } while (0)
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@ -233,52 +210,6 @@ static void sh64_icache_inv_user_page_range(struct mm_struct *mm,
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}
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}
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/*
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* Invalidate a small range of user context I-cache, not necessarily page
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* (or even cache-line) aligned.
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*
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* Since this is used inside ptrace, the ASID in the mm context typically
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* won't match current_asid. We'll have to switch ASID to do this. For
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* safety, and given that the range will be small, do all this under cli.
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*
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* Note, there is a hazard that the ASID in mm->context is no longer
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* actually associated with mm, i.e. if the mm->context has started a new
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* cycle since mm was last active. However, this is just a performance
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* issue: all that happens is that we invalidate lines belonging to
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* another mm, so the owning process has to refill them when that mm goes
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* live again. mm itself can't have any cache entries because there will
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* have been a flush_cache_all when the new mm->context cycle started.
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*/
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static void sh64_icache_inv_user_small_range(struct mm_struct *mm,
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unsigned long start, int len)
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{
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unsigned long long eaddr = start;
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unsigned long long eaddr_end = start + len;
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unsigned long current_asid, mm_asid;
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unsigned long flags;
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unsigned long long epage_start;
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/*
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* Align to start of cache line. Otherwise, suppose len==8 and
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* start was at 32N+28 : the last 4 bytes wouldn't get invalidated.
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*/
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eaddr = L1_CACHE_ALIGN(start);
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eaddr_end = start + len;
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mm_asid = cpu_asid(smp_processor_id(), mm);
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local_irq_save(flags);
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current_asid = switch_and_save_asid(mm_asid);
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epage_start = eaddr & PAGE_MASK;
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while (eaddr < eaddr_end) {
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__asm__ __volatile__("icbi %0, 0" : : "r" (eaddr));
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eaddr += L1_CACHE_BYTES;
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}
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switch_and_save_asid(current_asid);
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local_irq_restore(flags);
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}
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static void sh64_icache_inv_current_user_range(unsigned long start, unsigned long end)
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{
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/* The icbi instruction never raises ITLBMISS. i.e. if there's not a
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@ -564,7 +495,7 @@ static void sh64_dcache_purge_user_range(struct mm_struct *mm,
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* Invalidate the entire contents of both caches, after writing back to
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* memory any dirty data from the D-cache.
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*/
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void flush_cache_all(void)
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static void sh5_flush_cache_all(void)
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{
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sh64_dcache_purge_all();
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sh64_icache_inv_all();
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@ -591,7 +522,7 @@ void flush_cache_all(void)
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* I-cache. This is similar to the lack of action needed in
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* flush_tlb_mm - see fault.c.
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*/
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void flush_cache_mm(struct mm_struct *mm)
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static void sh5_flush_cache_mm(struct mm_struct *mm)
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{
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sh64_dcache_purge_all();
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}
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@ -603,8 +534,8 @@ void flush_cache_mm(struct mm_struct *mm)
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*
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* Note, 'end' is 1 byte beyond the end of the range to flush.
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*/
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void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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static void sh5_flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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@ -621,8 +552,8 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
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*
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* Note, this is called with pte lock held.
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*/
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void flush_cache_page(struct vm_area_struct *vma, unsigned long eaddr,
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unsigned long pfn)
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static void sh5_flush_cache_page(struct vm_area_struct *vma,
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unsigned long eaddr, unsigned long pfn)
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{
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sh64_dcache_purge_phy_page(pfn << PAGE_SHIFT);
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@ -630,7 +561,7 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long eaddr,
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sh64_icache_inv_user_page(vma, eaddr);
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}
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void flush_dcache_page(struct page *page)
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static void sh5_flush_dcache_page(struct page *page)
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{
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sh64_dcache_purge_phy_page(page_to_phys(page));
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wmb();
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@ -644,39 +575,20 @@ void flush_dcache_page(struct page *page)
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* mapping, therefore it's guaranteed that there no cache entries for
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* the range in cache sets of the wrong colour.
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*/
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void flush_icache_range(unsigned long start, unsigned long end)
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static void sh5_flush_icache_range(unsigned long start, unsigned long end)
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{
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__flush_purge_region((void *)start, end);
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wmb();
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sh64_icache_inv_kernel_range(start, end);
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}
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/*
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* Flush the range of user (defined by vma->vm_mm) address space starting
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* at 'addr' for 'len' bytes from the cache. The range does not straddle
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* a page boundary, the unique physical page containing the range is
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* 'page'. This seems to be used mainly for invalidating an address
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* range following a poke into the program text through the ptrace() call
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* from another process (e.g. for BRK instruction insertion).
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*/
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static void flush_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long addr, int len)
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{
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sh64_dcache_purge_coloured_phy_page(page_to_phys(page), addr);
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mb();
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if (vma->vm_flags & VM_EXEC)
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sh64_icache_inv_user_small_range(vma->vm_mm, addr, len);
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}
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/*
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* For the address range [start,end), write back the data from the
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* D-cache and invalidate the corresponding region of the I-cache for the
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* current process. Used to flush signal trampolines on the stack to
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* make them executable.
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*/
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void flush_cache_sigtramp(unsigned long vaddr)
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static void sh5_flush_cache_sigtramp(unsigned long vaddr)
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{
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unsigned long end = vaddr + L1_CACHE_BYTES;
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@ -685,138 +597,19 @@ void flush_cache_sigtramp(unsigned long vaddr)
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sh64_icache_inv_current_user_range(vaddr, end);
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}
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#ifdef CONFIG_MMU
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/*
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* These *MUST* lie in an area of virtual address space that's otherwise
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* unused.
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*/
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#define UNIQUE_EADDR_START 0xe0000000UL
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#define UNIQUE_EADDR_END 0xe8000000UL
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/*
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* Given a physical address paddr, and a user virtual address user_eaddr
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* which will eventually be mapped to it, create a one-off kernel-private
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* eaddr mapped to the same paddr. This is used for creating special
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* destination pages for copy_user_page and clear_user_page.
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*/
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static unsigned long sh64_make_unique_eaddr(unsigned long user_eaddr,
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unsigned long paddr)
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void __init sh5_cache_init(void)
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{
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static unsigned long current_pointer = UNIQUE_EADDR_START;
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unsigned long coloured_pointer;
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flush_cache_all = sh5_flush_cache_all;
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flush_cache_mm = sh5_flush_cache_mm;
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flush_cache_dup_mm = sh5_flush_cache_mm;
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flush_cache_page = sh5_flush_cache_page;
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flush_cache_range = sh5_flush_cache_range;
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flush_dcache_page = sh5_flush_dcache_page;
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flush_icache_range = sh5_flush_icache_range;
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flush_cache_sigtramp = sh5_flush_cache_sigtramp;
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if (current_pointer == UNIQUE_EADDR_END) {
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sh64_dcache_purge_all();
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current_pointer = UNIQUE_EADDR_START;
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}
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/* Reserve a slot for dcache colouring in the DTLB */
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dtlb_cache_slot = sh64_get_wired_dtlb_entry();
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coloured_pointer = (current_pointer & ~CACHE_OC_SYN_MASK) |
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(user_eaddr & CACHE_OC_SYN_MASK);
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sh64_setup_dtlb_cache_slot(coloured_pointer, get_asid(), paddr);
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current_pointer += (PAGE_SIZE << CACHE_OC_N_SYNBITS);
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return coloured_pointer;
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sh4__flush_region_init();
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}
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static void sh64_copy_user_page_coloured(void *to, void *from,
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unsigned long address)
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{
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void *coloured_to;
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/*
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* Discard any existing cache entries of the wrong colour. These are
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* present quite often, if the kernel has recently used the page
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* internally, then given it up, then it's been allocated to the user.
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*/
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sh64_dcache_purge_coloured_phy_page(__pa(to), (unsigned long)to);
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coloured_to = (void *)sh64_make_unique_eaddr(address, __pa(to));
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copy_page(from, coloured_to);
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sh64_teardown_dtlb_cache_slot();
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}
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static void sh64_clear_user_page_coloured(void *to, unsigned long address)
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{
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void *coloured_to;
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/*
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* Discard any existing kernel-originated lines of the wrong
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* colour (as above)
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*/
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sh64_dcache_purge_coloured_phy_page(__pa(to), (unsigned long)to);
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coloured_to = (void *)sh64_make_unique_eaddr(address, __pa(to));
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clear_page(coloured_to);
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sh64_teardown_dtlb_cache_slot();
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}
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/*
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* 'from' and 'to' are kernel virtual addresses (within the superpage
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* mapping of the physical RAM). 'address' is the user virtual address
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* where the copy 'to' will be mapped after. This allows a custom
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* mapping to be used to ensure that the new copy is placed in the
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* right cache sets for the user to see it without having to bounce it
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* out via memory. Note however : the call to flush_page_to_ram in
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* (generic)/mm/memory.c:(break_cow) undoes all this good work in that one
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* very important case!
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*
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* TBD : can we guarantee that on every call, any cache entries for
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* 'from' are in the same colour sets as 'address' also? i.e. is this
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* always used just to deal with COW? (I suspect not).
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*
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* There are two possibilities here for when the page 'from' was last accessed:
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* - by the kernel : this is OK, no purge required.
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* - by the/a user (e.g. for break_COW) : need to purge.
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*
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* If the potential user mapping at 'address' is the same colour as
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* 'from' there is no need to purge any cache lines from the 'from'
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* page mapped into cache sets of colour 'address'. (The copy will be
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* accessing the page through 'from').
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*/
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void copy_user_page(void *to, void *from, unsigned long address,
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struct page *page)
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{
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if (((address ^ (unsigned long) from) & CACHE_OC_SYN_MASK) != 0)
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sh64_dcache_purge_coloured_phy_page(__pa(from), address);
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if (((address ^ (unsigned long) to) & CACHE_OC_SYN_MASK) == 0)
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copy_page(to, from);
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else
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sh64_copy_user_page_coloured(to, from, address);
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}
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/*
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* 'to' is a kernel virtual address (within the superpage mapping of the
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* physical RAM). 'address' is the user virtual address where the 'to'
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* page will be mapped after. This allows a custom mapping to be used to
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* ensure that the new copy is placed in the right cache sets for the
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* user to see it without having to bounce it out via memory.
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*/
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void clear_user_page(void *to, unsigned long address, struct page *page)
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{
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if (((address ^ (unsigned long) to) & CACHE_OC_SYN_MASK) == 0)
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clear_page(to);
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else
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sh64_clear_user_page_coloured(to, address);
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}
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void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long vaddr, void *dst, const void *src,
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unsigned long len)
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{
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flush_cache_page(vma, vaddr, page_to_pfn(page));
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memcpy(dst, src, len);
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flush_icache_user_range(vma, page, vaddr, len);
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}
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void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long vaddr, void *dst, const void *src,
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unsigned long len)
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{
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flush_cache_page(vma, vaddr, page_to_pfn(page));
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memcpy(dst, src, len);
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}
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#endif
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@ -19,28 +19,19 @@ static void sh4__flush_wback_region(void *start, int size)
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cnt = (end - v) / L1_CACHE_BYTES;
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while (cnt >= 8) {
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbwb @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
__ocbwb(v); v += L1_CACHE_BYTES;
|
||||
__ocbwb(v); v += L1_CACHE_BYTES;
|
||||
__ocbwb(v); v += L1_CACHE_BYTES;
|
||||
__ocbwb(v); v += L1_CACHE_BYTES;
|
||||
__ocbwb(v); v += L1_CACHE_BYTES;
|
||||
__ocbwb(v); v += L1_CACHE_BYTES;
|
||||
__ocbwb(v); v += L1_CACHE_BYTES;
|
||||
__ocbwb(v); v += L1_CACHE_BYTES;
|
||||
cnt -= 8;
|
||||
}
|
||||
|
||||
while (cnt) {
|
||||
asm volatile("ocbwb @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
__ocbwb(v); v += L1_CACHE_BYTES;
|
||||
cnt--;
|
||||
}
|
||||
}
|
||||
|
|
@ -62,27 +53,18 @@ static void sh4__flush_purge_region(void *start, int size)
|
|||
cnt = (end - v) / L1_CACHE_BYTES;
|
||||
|
||||
while (cnt >= 8) {
|
||||
asm volatile("ocbp @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbp @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbp @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbp @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbp @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbp @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbp @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbp @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
__ocbp(v); v += L1_CACHE_BYTES;
|
||||
__ocbp(v); v += L1_CACHE_BYTES;
|
||||
__ocbp(v); v += L1_CACHE_BYTES;
|
||||
__ocbp(v); v += L1_CACHE_BYTES;
|
||||
__ocbp(v); v += L1_CACHE_BYTES;
|
||||
__ocbp(v); v += L1_CACHE_BYTES;
|
||||
__ocbp(v); v += L1_CACHE_BYTES;
|
||||
__ocbp(v); v += L1_CACHE_BYTES;
|
||||
cnt -= 8;
|
||||
}
|
||||
while (cnt) {
|
||||
asm volatile("ocbp @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
__ocbp(v); v += L1_CACHE_BYTES;
|
||||
cnt--;
|
||||
}
|
||||
}
|
||||
|
|
@ -101,28 +83,19 @@ static void sh4__flush_invalidate_region(void *start, int size)
|
|||
cnt = (end - v) / L1_CACHE_BYTES;
|
||||
|
||||
while (cnt >= 8) {
|
||||
asm volatile("ocbi @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbi @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbi @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbi @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbi @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbi @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbi @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
asm volatile("ocbi @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
__ocbi(v); v += L1_CACHE_BYTES;
|
||||
__ocbi(v); v += L1_CACHE_BYTES;
|
||||
__ocbi(v); v += L1_CACHE_BYTES;
|
||||
__ocbi(v); v += L1_CACHE_BYTES;
|
||||
__ocbi(v); v += L1_CACHE_BYTES;
|
||||
__ocbi(v); v += L1_CACHE_BYTES;
|
||||
__ocbi(v); v += L1_CACHE_BYTES;
|
||||
__ocbi(v); v += L1_CACHE_BYTES;
|
||||
cnt -= 8;
|
||||
}
|
||||
|
||||
while (cnt) {
|
||||
asm volatile("ocbi @%0" : : "r" (v));
|
||||
v += L1_CACHE_BYTES;
|
||||
__ocbi(v); v += L1_CACHE_BYTES;
|
||||
cnt--;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue