drm/i915/skl: Implementation of SKL display power well support
This patch implements core logic of SKL display power well. v2: Addressed Imre's comments - Added respective DDIs under power well #1 and #2 - Simplified repetitive code in power well programming v3: Implemented Imre's comments - Further simplified power well programming - Made sure that PW 1 is enabled prior to PW 2 v4: Fix minor conflict with the the cherryview support (Damien) v5: Add the PLL power domain to the always on power well (Damien) v6: Disable BIOS power well (Imre) Use power well data for comparison (Imre) Put the PLL power domain into PW1 as its needed for CDCLK (Satheesh, Damien) v7: Addressed Imre's comments - Lowered the time out to 1ms - Added parantheses in macro - Moved debug message and fixed wait_for interval v8: - Add a WARN() when swiching on an unknown power well (Imre, done by Damien) - Whitespace fixes (spaces instead of tabs) (Damien) v9: (Imre, done by Damien) - Merge the register definitions with this patch - Merge the MISC IO power well in this patch v10: (Imre, done by Damien) - Define the Misc I/O power domains to be the power well 1 ones as Misc I/O needs to be enabled with PW1 - Added Transcoder A and VGA domains to PW 2 - Remove the MISC_IO power domains as well in the the always on domains definition - Move Misc I/O power well at the top of the power well list so it's turned on right after PW1. Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v3,v6,v7) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Satheeshakrishna M
Daniel Vetter
parent
afd65eb4cc
commit
94dd5138c5
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@ -586,6 +586,19 @@ enum punit_power_well {
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PUNIT_POWER_WELL_NUM,
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};
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enum skl_disp_power_wells {
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SKL_DISP_PW_MISC_IO,
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SKL_DISP_PW_DDI_A_E,
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SKL_DISP_PW_DDI_B,
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SKL_DISP_PW_DDI_C,
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SKL_DISP_PW_DDI_D,
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SKL_DISP_PW_1 = 14,
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SKL_DISP_PW_2,
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};
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#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
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#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
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#define PUNIT_REG_PWRGT_CTRL 0x60
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#define PUNIT_REG_PWRGT_STATUS 0x61
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#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
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@ -6351,6 +6364,13 @@ enum punit_power_well {
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#define HSW_PWR_WELL_FORCE_ON (1<<19)
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#define HSW_PWR_WELL_CTL6 0x45414
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/* SKL Fuse Status */
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#define SKL_FUSE_STATUS 0x42000
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#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
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#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
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#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
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#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
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/* Per-pipe DDI Function Control */
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#define TRANS_DDI_FUNC_CTL_A 0x60400
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#define TRANS_DDI_FUNC_CTL_B 0x61400
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@ -230,6 +230,136 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
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}
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}
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#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_TRANSCODER_A) | \
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BIT(POWER_DOMAIN_PIPE_B) | \
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BIT(POWER_DOMAIN_TRANSCODER_B) | \
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BIT(POWER_DOMAIN_PIPE_C) | \
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BIT(POWER_DOMAIN_TRANSCODER_C) | \
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BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
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BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
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BIT(POWER_DOMAIN_AUX_B) | \
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BIT(POWER_DOMAIN_AUX_C) | \
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BIT(POWER_DOMAIN_AUX_D) | \
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BIT(POWER_DOMAIN_AUDIO) | \
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BIT(POWER_DOMAIN_VGA) | \
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BIT(POWER_DOMAIN_INIT))
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#define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
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SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
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BIT(POWER_DOMAIN_PLLS) | \
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BIT(POWER_DOMAIN_PIPE_A) | \
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BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
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BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
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BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
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BIT(POWER_DOMAIN_AUX_A) | \
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BIT(POWER_DOMAIN_INIT))
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#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
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BIT(POWER_DOMAIN_INIT))
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#define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
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BIT(POWER_DOMAIN_INIT))
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#define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
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BIT(POWER_DOMAIN_INIT))
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#define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
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BIT(POWER_DOMAIN_INIT))
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#define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \
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SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS)
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#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
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(POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
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SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
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SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \
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SKL_DISPLAY_DDI_B_POWER_DOMAINS | \
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SKL_DISPLAY_DDI_C_POWER_DOMAINS | \
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SKL_DISPLAY_DDI_D_POWER_DOMAINS | \
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SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \
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BIT(POWER_DOMAIN_INIT))
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static void skl_set_power_well(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well, bool enable)
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{
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uint32_t tmp, fuse_status;
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uint32_t req_mask, state_mask;
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bool check_fuse_status = false;
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tmp = I915_READ(HSW_PWR_WELL_DRIVER);
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fuse_status = I915_READ(SKL_FUSE_STATUS);
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switch (power_well->data) {
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case SKL_DISP_PW_1:
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if (wait_for((I915_READ(SKL_FUSE_STATUS) &
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SKL_FUSE_PG0_DIST_STATUS), 1)) {
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DRM_ERROR("PG0 not enabled\n");
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return;
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}
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break;
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case SKL_DISP_PW_2:
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if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
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DRM_ERROR("PG1 in disabled state\n");
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return;
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}
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break;
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case SKL_DISP_PW_DDI_A_E:
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case SKL_DISP_PW_DDI_B:
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case SKL_DISP_PW_DDI_C:
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case SKL_DISP_PW_DDI_D:
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case SKL_DISP_PW_MISC_IO:
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break;
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default:
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WARN(1, "Unknown power well %lu\n", power_well->data);
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return;
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}
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req_mask = SKL_POWER_WELL_REQ(power_well->data);
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state_mask = SKL_POWER_WELL_STATE(power_well->data);
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if (enable) {
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if (!(tmp & req_mask)) {
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I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
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DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
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}
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if (!(tmp & state_mask)) {
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if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
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state_mask), 1))
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DRM_ERROR("%s enable timeout\n",
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power_well->name);
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check_fuse_status = true;
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}
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} else {
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if (tmp & req_mask) {
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I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
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POSTING_READ(HSW_PWR_WELL_DRIVER);
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DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
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}
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}
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if (check_fuse_status) {
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if (power_well->data == SKL_DISP_PW_1) {
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if (wait_for((I915_READ(SKL_FUSE_STATUS) &
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SKL_FUSE_PG1_DIST_STATUS), 1))
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DRM_ERROR("PG1 distributing status timeout\n");
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} else if (power_well->data == SKL_DISP_PW_2) {
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if (wait_for((I915_READ(SKL_FUSE_STATUS) &
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SKL_FUSE_PG2_DIST_STATUS), 1))
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DRM_ERROR("PG2 distributing status timeout\n");
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}
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}
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}
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static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well)
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{
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@ -255,6 +385,36 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
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hsw_set_power_well(dev_priv, power_well, false);
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}
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static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well)
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{
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uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
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SKL_POWER_WELL_STATE(power_well->data);
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return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
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}
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static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well)
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{
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skl_set_power_well(dev_priv, power_well, power_well->count > 0);
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/* Clear any request made by BIOS as driver is taking over */
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I915_WRITE(HSW_PWR_WELL_BIOS, 0);
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}
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static void skl_power_well_enable(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well)
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{
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skl_set_power_well(dev_priv, power_well, true);
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}
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static void skl_power_well_disable(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well)
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{
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skl_set_power_well(dev_priv, power_well, false);
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}
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static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well)
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{
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@ -829,6 +989,13 @@ static const struct i915_power_well_ops hsw_power_well_ops = {
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.is_enabled = hsw_power_well_enabled,
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};
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static const struct i915_power_well_ops skl_power_well_ops = {
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.sync_hw = skl_power_well_sync_hw,
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.enable = skl_power_well_enable,
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.disable = skl_power_well_disable,
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.is_enabled = skl_power_well_enabled,
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};
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static struct i915_power_well hsw_power_wells[] = {
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{
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.name = "always-on",
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@ -1059,6 +1226,57 @@ static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_pr
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return NULL;
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}
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static struct i915_power_well skl_power_wells[] = {
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{
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.name = "always-on",
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.always_on = 1,
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.domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
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.ops = &i9xx_always_on_power_well_ops,
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},
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{
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.name = "power well 1",
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.domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.data = SKL_DISP_PW_1,
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},
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{
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.name = "MISC IO power well",
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.domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.data = SKL_DISP_PW_MISC_IO,
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},
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{
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.name = "power well 2",
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.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.data = SKL_DISP_PW_2,
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},
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{
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.name = "DDI A/E power well",
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.domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.data = SKL_DISP_PW_DDI_A_E,
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},
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{
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.name = "DDI B power well",
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.domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.data = SKL_DISP_PW_DDI_B,
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},
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{
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.name = "DDI C power well",
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.domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.data = SKL_DISP_PW_DDI_C,
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},
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{
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.name = "DDI D power well",
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.domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.data = SKL_DISP_PW_DDI_D,
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},
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};
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#define set_power_wells(power_domains, __power_wells) ({ \
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(power_domains)->power_wells = (__power_wells); \
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(power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
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@ -1085,6 +1303,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
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set_power_wells(power_domains, hsw_power_wells);
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} else if (IS_BROADWELL(dev_priv->dev)) {
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set_power_wells(power_domains, bdw_power_wells);
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} else if (IS_SKYLAKE(dev_priv->dev)) {
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set_power_wells(power_domains, skl_power_wells);
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} else if (IS_CHERRYVIEW(dev_priv->dev)) {
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set_power_wells(power_domains, chv_power_wells);
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} else if (IS_VALLEYVIEW(dev_priv->dev)) {
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