be2net: Use TXQ_CREATE_V2 cmd
Skyhawk-R and BE3-R (SuperNIC profile) require V2 version of TXQ_CREATE cmd to be used. Signed-off-by: Vasundhara Volam <vasundhara.volam@emulex.com> Signed-off-by: Sathya Perla <sathya.perla@emulex.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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26f26b3a64
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@ -214,6 +214,7 @@ struct be_tx_stats {
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};
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struct be_tx_obj {
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u32 db_offset;
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struct be_queue_info q;
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struct be_queue_info cq;
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/* Remember the skbs that were transmitted */
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@ -1095,15 +1095,14 @@ int be_cmd_mccq_create(struct be_adapter *adapter,
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return status;
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}
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int be_cmd_txq_create(struct be_adapter *adapter,
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struct be_queue_info *txq,
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struct be_queue_info *cq)
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int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
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{
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struct be_mcc_wrb *wrb;
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struct be_cmd_req_eth_tx_create *req;
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struct be_queue_info *txq = &txo->q;
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struct be_queue_info *cq = &txo->cq;
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struct be_dma_mem *q_mem = &txq->dma_mem;
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void *ctxt;
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int status;
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int status, ver = 0;
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spin_lock_bh(&adapter->mcc_lock);
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@ -1114,34 +1113,37 @@ int be_cmd_txq_create(struct be_adapter *adapter,
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}
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req = embedded_payload(wrb);
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ctxt = &req->context;
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be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
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OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
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if (lancer_chip(adapter)) {
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req->hdr.version = 1;
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AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
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adapter->if_handle);
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req->if_id = cpu_to_le16(adapter->if_handle);
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} else if (BEx_chip(adapter)) {
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if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
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req->hdr.version = 2;
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} else { /* For SH */
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req->hdr.version = 2;
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}
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req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
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req->ulp_num = BE_ULP1_NUM;
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req->type = BE_ETH_TX_RING_TYPE_STANDARD;
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AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
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be_encoded_q_len(txq->len));
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AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
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AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
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be_dws_cpu_to_le(ctxt, sizeof(req->context));
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req->cq_id = cpu_to_le16(cq->id);
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req->queue_size = be_encoded_q_len(txq->len);
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be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
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ver = req->hdr.version;
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status = be_mcc_notify_wait(adapter);
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if (!status) {
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struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
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txq->id = le16_to_cpu(resp->cid);
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if (ver == 2)
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txo->db_offset = le32_to_cpu(resp->db_offset);
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else
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txo->db_offset = DB_TXULP1_OFFSET;
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txq->created = true;
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}
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@ -474,46 +474,27 @@ struct be_cmd_resp_mcc_create {
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#define BE_ETH_TX_RING_TYPE_STANDARD 2
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#define BE_ULP1_NUM 1
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/* Pseudo amap definition in which each bit of the actual structure is defined
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* as a byte: used to calculate offset/shift/mask of each field */
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struct amap_tx_context {
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u8 if_id[16]; /* dword 0 */
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u8 tx_ring_size[4]; /* dword 0 */
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u8 rsvd1[26]; /* dword 0 */
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u8 pci_func_id[8]; /* dword 1 */
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u8 rsvd2[9]; /* dword 1 */
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u8 ctx_valid; /* dword 1 */
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u8 cq_id_send[16]; /* dword 2 */
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u8 rsvd3[16]; /* dword 2 */
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u8 rsvd4[32]; /* dword 3 */
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u8 rsvd5[32]; /* dword 4 */
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u8 rsvd6[32]; /* dword 5 */
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u8 rsvd7[32]; /* dword 6 */
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u8 rsvd8[32]; /* dword 7 */
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u8 rsvd9[32]; /* dword 8 */
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u8 rsvd10[32]; /* dword 9 */
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u8 rsvd11[32]; /* dword 10 */
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u8 rsvd12[32]; /* dword 11 */
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u8 rsvd13[32]; /* dword 12 */
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u8 rsvd14[32]; /* dword 13 */
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u8 rsvd15[32]; /* dword 14 */
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u8 rsvd16[32]; /* dword 15 */
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} __packed;
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struct be_cmd_req_eth_tx_create {
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struct be_cmd_req_hdr hdr;
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u8 num_pages;
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u8 ulp_num;
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u8 type;
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u8 bound_port;
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u8 context[sizeof(struct amap_tx_context) / 8];
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u16 type;
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u16 if_id;
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u8 queue_size;
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u8 rsvd0;
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u32 rsvd1;
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u16 cq_id;
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u16 rsvd2;
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u32 rsvd3[13];
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struct phys_addr pages[8];
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} __packed;
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struct be_cmd_resp_eth_tx_create {
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struct be_cmd_resp_hdr hdr;
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u16 cid;
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u16 rsvd0;
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u16 rid;
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u32 db_offset;
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u32 rsvd0[4];
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} __packed;
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/******************** Create RxQ ***************************/
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@ -1067,7 +1048,6 @@ struct be_cmd_resp_modify_eq_delay {
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} __packed;
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/******************** Get FW Config *******************/
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#define BE_FUNCTION_CAPS_RSS 0x2
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/* The HW can come up in either of the following multi-channel modes
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* based on the skew/IPL.
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*/
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@ -1841,8 +1821,7 @@ extern int be_cmd_mccq_create(struct be_adapter *adapter,
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struct be_queue_info *mccq,
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struct be_queue_info *cq);
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extern int be_cmd_txq_create(struct be_adapter *adapter,
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struct be_queue_info *txq,
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struct be_queue_info *cq);
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struct be_tx_obj *txo);
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extern int be_cmd_rxq_create(struct be_adapter *adapter,
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struct be_queue_info *rxq, u16 cq_id,
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u16 frag_size, u32 if_id, u32 rss, u8 *rss_id);
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@ -72,6 +72,10 @@
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*/
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#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
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/********* PCI Function Capability *********/
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#define BE_FUNCTION_CAPS_RSS 0x2
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#define BE_FUNCTION_CAPS_SUPER_NIC 0x40
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/********* Power management (WOL) **********/
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#define PCICFG_PM_CONTROL_OFFSET 0x44
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#define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
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@ -197,14 +197,15 @@ static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
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iowrite32(val, adapter->db + DB_RQ_OFFSET);
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}
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static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
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static void be_txq_notify(struct be_adapter *adapter, struct be_tx_obj *txo,
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u16 posted)
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{
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u32 val = 0;
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val |= qid & DB_TXULP_RING_ID_MASK;
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val |= txo->q.id & DB_TXULP_RING_ID_MASK;
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val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
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wmb();
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iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
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iowrite32(val, adapter->db + txo->db_offset);
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}
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static void be_eq_notify(struct be_adapter *adapter, u16 qid,
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@ -833,7 +834,7 @@ static netdev_tx_t be_xmit(struct sk_buff *skb,
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stopped = true;
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}
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be_txq_notify(adapter, txq->id, wrb_cnt);
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be_txq_notify(adapter, txo, wrb_cnt);
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be_tx_stats_update(txo, wrb_cnt, copied, gso_segs, stopped);
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} else {
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@ -1969,7 +1970,7 @@ static int be_tx_qs_create(struct be_adapter *adapter)
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if (status)
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return status;
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status = be_cmd_txq_create(adapter, &txo->q, &txo->cq);
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status = be_cmd_txq_create(adapter, txo);
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if (status)
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return status;
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}
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