ASoC: cs42l83: Extend CS42L42 support to new part
The CS42L83 part is a headphone jack codec found in recent Apple machines. It is a publicly undocumented part but as far as can be told it is identical to CS42L42 except for two points: * The chip ID is different. * Of those registers for which we have a default value in the existing CS42L42 kernel driver, one register (MCLK_CTL) differs in its reset value on CS42L83. To address those two points (and only those), add to the CS42L42 driver a separate CS42L83 front. Signed-off-by: Martin Povišer <povik+lin@cutebit.org> Link: https://lore.kernel.org/r/20220915094444.11434-10-povik+lin@cutebit.org Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Martin Povišer
Mark Brown
parent
30b679e2cb
commit
94d5f62a91
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@ -1906,6 +1906,7 @@ L: alsa-devel@alsa-project.org (moderated for non-subscribers)
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S: Maintained
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F: Documentation/devicetree/bindings/sound/apple,*
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F: sound/soc/apple/*
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F: sound/soc/codecs/cs42l83-i2c.c
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ARM/ARTPEC MACHINE SUPPORT
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M: Jesper Nilsson <jesper.nilsson@axis.com>
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@ -40,6 +40,7 @@
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#define CS42L42_PAGE_30 0x3000
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#define CS42L42_CHIP_ID 0x42A42
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#define CS42L83_CHIP_ID 0x42A83
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/* Page 0x10 Global Registers */
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#define CS42L42_DEVID_AB (CS42L42_PAGE_10 + 0x01)
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@ -722,6 +722,13 @@ config SND_SOC_CS42L73
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tristate "Cirrus Logic CS42L73 CODEC"
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depends on I2C
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config SND_SOC_CS42L83
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tristate "Cirrus Logic CS42L83 CODEC"
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depends on I2C
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select REGMAP
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select REGMAP_I2C
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select SND_SOC_CS42L42_CORE
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config SND_SOC_CS4234
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tristate "Cirrus Logic CS4234 CODEC"
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depends on I2C
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@ -71,6 +71,7 @@ snd-soc-cs42l51-i2c-objs := cs42l51-i2c.o
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snd-soc-cs42l52-objs := cs42l52.o
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snd-soc-cs42l56-objs := cs42l56.o
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snd-soc-cs42l73-objs := cs42l73.o
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snd-soc-cs42l83-i2c-objs := cs42l83-i2c.o
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snd-soc-cs4234-objs := cs4234.o
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snd-soc-cs4265-objs := cs4265.o
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snd-soc-cs4270-objs := cs4270.o
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@ -430,6 +431,7 @@ obj-$(CONFIG_SND_SOC_CS42L51_I2C) += snd-soc-cs42l51-i2c.o
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obj-$(CONFIG_SND_SOC_CS42L52) += snd-soc-cs42l52.o
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obj-$(CONFIG_SND_SOC_CS42L56) += snd-soc-cs42l56.o
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obj-$(CONFIG_SND_SOC_CS42L73) += snd-soc-cs42l73.o
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obj-$(CONFIG_SND_SOC_CS42L83) += snd-soc-cs42l83-i2c.o
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obj-$(CONFIG_SND_SOC_CS4234) += snd-soc-cs4234.o
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obj-$(CONFIG_SND_SOC_CS4265) += snd-soc-cs4265.o
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obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o
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@ -31,6 +31,7 @@ static int cs42l42_i2c_probe(struct i2c_client *i2c_client)
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return ret;
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}
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cs42l42->devid = CS42L42_CHIP_ID;
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cs42l42->dev = dev;
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cs42l42->regmap = regmap;
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cs42l42->irq = i2c_client->irq;
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@ -2318,11 +2318,11 @@ int cs42l42_init(struct cs42l42_private *cs42l42)
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goto err_disable;
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}
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if (devid != CS42L42_CHIP_ID) {
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if (devid != cs42l42->devid) {
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ret = -ENODEV;
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dev_err(cs42l42->dev,
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"CS42L42 Device ID (%X). Expected %X\n",
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devid, CS42L42_CHIP_ID);
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"CS42L%x Device ID (%X). Expected %X\n",
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cs42l42->devid & 0xff, devid, cs42l42->devid);
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goto err_disable;
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}
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@ -2333,7 +2333,8 @@ int cs42l42_init(struct cs42l42_private *cs42l42)
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}
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dev_info(cs42l42->dev,
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"Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
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"Cirrus Logic CS42L%x, Revision: %02X\n",
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cs42l42->devid & 0xff, reg & 0xFF);
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/* Power up the codec */
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regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
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@ -31,6 +31,7 @@ struct cs42l42_private {
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struct completion pdn_done;
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struct snd_soc_jack *jack;
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struct mutex irq_lock;
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int devid;
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int irq;
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int pll_config;
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u32 sclk;
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@ -0,0 +1,242 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* cs42l83-i2c.c -- CS42L83 ALSA SoC audio driver for I2C
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*
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* Based on cs42l42-i2c.c:
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* Copyright 2016, 2022 Cirrus Logic, Inc.
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*/
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include "cs42l42.h"
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static const struct reg_default cs42l83_reg_defaults[] = {
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{ CS42L42_FRZ_CTL, 0x00 },
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{ CS42L42_SRC_CTL, 0x10 },
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{ CS42L42_MCLK_CTL, 0x00 }, /* <- only deviation from CS42L42 */
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{ CS42L42_SFTRAMP_RATE, 0xA4 },
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{ CS42L42_SLOW_START_ENABLE, 0x70 },
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{ CS42L42_I2C_DEBOUNCE, 0x88 },
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{ CS42L42_I2C_STRETCH, 0x03 },
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{ CS42L42_I2C_TIMEOUT, 0xB7 },
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{ CS42L42_PWR_CTL1, 0xFF },
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{ CS42L42_PWR_CTL2, 0x84 },
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{ CS42L42_PWR_CTL3, 0x20 },
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{ CS42L42_RSENSE_CTL1, 0x40 },
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{ CS42L42_RSENSE_CTL2, 0x00 },
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{ CS42L42_OSC_SWITCH, 0x00 },
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{ CS42L42_RSENSE_CTL3, 0x1B },
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{ CS42L42_TSENSE_CTL, 0x1B },
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{ CS42L42_TSRS_INT_DISABLE, 0x00 },
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{ CS42L42_HSDET_CTL1, 0x77 },
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{ CS42L42_HSDET_CTL2, 0x00 },
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{ CS42L42_HS_SWITCH_CTL, 0xF3 },
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{ CS42L42_HS_CLAMP_DISABLE, 0x00 },
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{ CS42L42_MCLK_SRC_SEL, 0x00 },
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{ CS42L42_SPDIF_CLK_CFG, 0x00 },
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{ CS42L42_FSYNC_PW_LOWER, 0x00 },
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{ CS42L42_FSYNC_PW_UPPER, 0x00 },
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{ CS42L42_FSYNC_P_LOWER, 0xF9 },
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{ CS42L42_FSYNC_P_UPPER, 0x00 },
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{ CS42L42_ASP_CLK_CFG, 0x00 },
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{ CS42L42_ASP_FRM_CFG, 0x10 },
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{ CS42L42_FS_RATE_EN, 0x00 },
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{ CS42L42_IN_ASRC_CLK, 0x00 },
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{ CS42L42_OUT_ASRC_CLK, 0x00 },
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{ CS42L42_PLL_DIV_CFG1, 0x00 },
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{ CS42L42_ADC_OVFL_INT_MASK, 0x01 },
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{ CS42L42_MIXER_INT_MASK, 0x0F },
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{ CS42L42_SRC_INT_MASK, 0x0F },
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{ CS42L42_ASP_RX_INT_MASK, 0x1F },
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{ CS42L42_ASP_TX_INT_MASK, 0x0F },
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{ CS42L42_CODEC_INT_MASK, 0x03 },
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{ CS42L42_SRCPL_INT_MASK, 0x7F },
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{ CS42L42_VPMON_INT_MASK, 0x01 },
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{ CS42L42_PLL_LOCK_INT_MASK, 0x01 },
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{ CS42L42_TSRS_PLUG_INT_MASK, 0x0F },
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{ CS42L42_PLL_CTL1, 0x00 },
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{ CS42L42_PLL_DIV_FRAC0, 0x00 },
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{ CS42L42_PLL_DIV_FRAC1, 0x00 },
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{ CS42L42_PLL_DIV_FRAC2, 0x00 },
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{ CS42L42_PLL_DIV_INT, 0x40 },
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{ CS42L42_PLL_CTL3, 0x10 },
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{ CS42L42_PLL_CAL_RATIO, 0x80 },
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{ CS42L42_PLL_CTL4, 0x03 },
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{ CS42L42_LOAD_DET_EN, 0x00 },
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{ CS42L42_HSBIAS_SC_AUTOCTL, 0x03 },
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{ CS42L42_WAKE_CTL, 0xC0 },
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{ CS42L42_ADC_DISABLE_MUTE, 0x00 },
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{ CS42L42_TIPSENSE_CTL, 0x02 },
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{ CS42L42_MISC_DET_CTL, 0x03 },
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{ CS42L42_MIC_DET_CTL1, 0x1F },
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{ CS42L42_MIC_DET_CTL2, 0x2F },
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{ CS42L42_DET_INT1_MASK, 0xE0 },
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{ CS42L42_DET_INT2_MASK, 0xFF },
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{ CS42L42_HS_BIAS_CTL, 0xC2 },
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{ CS42L42_ADC_CTL, 0x00 },
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{ CS42L42_ADC_VOLUME, 0x00 },
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{ CS42L42_ADC_WNF_HPF_CTL, 0x71 },
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{ CS42L42_DAC_CTL1, 0x00 },
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{ CS42L42_DAC_CTL2, 0x02 },
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{ CS42L42_HP_CTL, 0x0D },
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{ CS42L42_CLASSH_CTL, 0x07 },
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{ CS42L42_MIXER_CHA_VOL, 0x3F },
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{ CS42L42_MIXER_ADC_VOL, 0x3F },
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{ CS42L42_MIXER_CHB_VOL, 0x3F },
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{ CS42L42_EQ_COEF_IN0, 0x00 },
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{ CS42L42_EQ_COEF_IN1, 0x00 },
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{ CS42L42_EQ_COEF_IN2, 0x00 },
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{ CS42L42_EQ_COEF_IN3, 0x00 },
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{ CS42L42_EQ_COEF_RW, 0x00 },
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{ CS42L42_EQ_COEF_OUT0, 0x00 },
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{ CS42L42_EQ_COEF_OUT1, 0x00 },
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{ CS42L42_EQ_COEF_OUT2, 0x00 },
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{ CS42L42_EQ_COEF_OUT3, 0x00 },
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{ CS42L42_EQ_INIT_STAT, 0x00 },
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{ CS42L42_EQ_START_FILT, 0x00 },
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{ CS42L42_EQ_MUTE_CTL, 0x00 },
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{ CS42L42_SP_RX_CH_SEL, 0x04 },
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{ CS42L42_SP_RX_ISOC_CTL, 0x04 },
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{ CS42L42_SP_RX_FS, 0x8C },
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{ CS42l42_SPDIF_CH_SEL, 0x0E },
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{ CS42L42_SP_TX_ISOC_CTL, 0x04 },
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{ CS42L42_SP_TX_FS, 0xCC },
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{ CS42L42_SPDIF_SW_CTL1, 0x3F },
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{ CS42L42_SRC_SDIN_FS, 0x40 },
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{ CS42L42_SRC_SDOUT_FS, 0x40 },
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{ CS42L42_SPDIF_CTL1, 0x01 },
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{ CS42L42_SPDIF_CTL2, 0x00 },
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{ CS42L42_SPDIF_CTL3, 0x00 },
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{ CS42L42_SPDIF_CTL4, 0x42 },
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{ CS42L42_ASP_TX_SZ_EN, 0x00 },
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{ CS42L42_ASP_TX_CH_EN, 0x00 },
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{ CS42L42_ASP_TX_CH_AP_RES, 0x0F },
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{ CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
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{ CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
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{ CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 },
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{ CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 },
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{ CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 },
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{ CS42L42_ASP_RX_DAI0_EN, 0x00 },
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{ CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 },
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{ CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
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{ CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
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{ CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 },
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{ CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
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{ CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 },
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{ CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 },
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{ CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
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{ CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 },
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{ CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 },
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{ CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
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{ CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 },
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{ CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 },
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{ CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 },
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{ CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 },
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{ CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 },
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{ CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 },
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{ CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 },
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};
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/*
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* This is all the same as for CS42L42 but we
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* replace the on-reset register defaults.
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*/
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const struct regmap_config cs42l83_regmap = {
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.reg_bits = 8,
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.val_bits = 8,
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.readable_reg = cs42l42_readable_register,
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.volatile_reg = cs42l42_volatile_register,
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.ranges = &cs42l42_page_range,
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.num_ranges = 1,
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.max_register = CS42L42_MAX_REGISTER,
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.reg_defaults = cs42l83_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(cs42l83_reg_defaults),
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.cache_type = REGCACHE_RBTREE,
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.use_single_read = true,
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.use_single_write = true,
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};
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static int cs42l83_i2c_probe(struct i2c_client *i2c_client)
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{
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struct device *dev = &i2c_client->dev;
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struct cs42l42_private *cs42l83;
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struct regmap *regmap;
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int ret;
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cs42l83 = devm_kzalloc(dev, sizeof(*cs42l83), GFP_KERNEL);
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if (!cs42l83)
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return -ENOMEM;
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regmap = devm_regmap_init_i2c(i2c_client, &cs42l83_regmap);
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if (IS_ERR(regmap))
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return dev_err_probe(&i2c_client->dev, PTR_ERR(regmap),
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"regmap_init() failed\n");
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cs42l83->devid = CS42L83_CHIP_ID;
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cs42l83->dev = dev;
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cs42l83->regmap = regmap;
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cs42l83->irq = i2c_client->irq;
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ret = cs42l42_common_probe(cs42l83, &cs42l42_soc_component, &cs42l42_dai);
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if (ret)
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return ret;
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return cs42l42_init(cs42l83);
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}
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static int cs42l83_i2c_remove(struct i2c_client *i2c_client)
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{
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struct cs42l42_private *cs42l83 = dev_get_drvdata(&i2c_client->dev);
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cs42l42_common_remove(cs42l83);
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return 0;
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}
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static int __maybe_unused cs42l83_i2c_resume(struct device *dev)
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{
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int ret;
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ret = cs42l42_resume(dev);
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if (ret)
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return ret;
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cs42l42_resume_restore(dev);
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return 0;
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}
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static const struct dev_pm_ops cs42l83_i2c_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(cs42l42_suspend, cs42l83_i2c_resume)
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};
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static const struct of_device_id __maybe_unused cs42l83_of_match[] = {
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{ .compatible = "cirrus,cs42l83", },
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{}
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};
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MODULE_DEVICE_TABLE(of, cs42l83_of_match);
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static struct i2c_driver cs42l83_i2c_driver = {
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.driver = {
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.name = "cs42l83",
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.pm = &cs42l83_i2c_pm_ops,
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.of_match_table = of_match_ptr(cs42l83_of_match),
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},
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.probe_new = cs42l83_i2c_probe,
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.remove = cs42l83_i2c_remove,
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};
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module_i2c_driver(cs42l83_i2c_driver);
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MODULE_DESCRIPTION("ASoC CS42L83 I2C driver");
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MODULE_AUTHOR("Martin Povišer <povik+lin@cutebit.org>");
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MODULE_LICENSE("GPL");
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MODULE_IMPORT_NS(SND_SOC_CS42L42_CORE);
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