Phytium JPEG Encoder driver
Support for the Phytium JPEG Encoder Engine embedded in the Phytium SOCs.The engine can capture and compress video data from digital or analog sources.
Reviewed-by:maohongbo<maohongbo@phytium.com.cn>
Signed-off-by: Wang Min <wangmin@phytium.com.cn>
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
(cherry picked from commit 6f9e10130c)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
This commit is contained in:
xuyan
Jianping Liu
parent
d978e4cfa4
commit
94c9fd89fc
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@ -2096,6 +2096,7 @@ W: https://www.phytium.com.cn
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F: arch/arm64/boot/dts/phytium/*
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F: Documentation/devicetree/bindings/net/can/phytium-can.txt
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F: drivers/net/can/phytium/*
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F: drivers/media/platform/phytium-jpeg/phytium_jpeg*
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ARM/PLEB SUPPORT
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M: Peter Chubb <pleb@gelato.unsw.edu.au>
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@ -160,6 +160,16 @@ config VIDEO_TI_CAL
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In TI Technical Reference Manual this module is referred as
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Camera Interface Subsystem (CAMSS).
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config VIDEO_PHYTIUM_JPEG
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tristate "Phytium JPEG Encoder driver"
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depends on VIDEO_V4L2
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select VIDEOBUF2_DMA_CONTIG
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help
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Support for the Phytium JPEG Encoder Engine embedded
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in the Phytium SOCs.
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The engine can capture and compress video data from
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digital or analog sources.
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endif # V4L_PLATFORM_DRIVERS
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menuconfig V4L_MEM2MEM_DRIVERS
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@ -96,6 +96,8 @@ obj-$(CONFIG_VIDEO_QCOM_CAMSS) += qcom/camss/
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obj-$(CONFIG_VIDEO_QCOM_VENUS) += qcom/venus/
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obj-$(CONFIG_VIDEO_PHYTIUM_JPEG) += phytium-jpeg/
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obj-y += meson/
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obj-y += cros-ec-cec/
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-only
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phytium_jpeg-objs := phytium_jpeg_core.o
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obj-$(CONFIG_VIDEO_PHYTIUM_JPEG) += phytium_jpeg.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,147 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2021-2023, Phytium Technology Co., Ltd.
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*/
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#ifndef _PHYTIUM_JPEG_CORE_H
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#define _PHYTIUM_JPEG_CORE_H
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#include <linux/atomic.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_reserved_mem.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/v4l2-controls.h>
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#include <linux/videodev2.h>
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#include <linux/wait.h>
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#include <linux/workqueue.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-dev.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-dv-timings.h>
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#include <media/v4l2-event.h>
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#include <media/v4l2-ioctl.h>
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#include <media/videobuf2-dma-contig.h>
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#define PHYTIUM_JPEG_NAME "phytium-jpeg"
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#define MAX_FRAME_RATE 60
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#define MAX_HEIGHT 1080
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#define MAX_WIDTH 1920
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#define MIN_HEIGHT 480
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#define MIN_WIDTH 640
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#define MIN_PIXEL_CLOCK (640 * 480 * 60) /* 640 x 480 x 60Hz */
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#define MAX_PIXEL_CLOCK (1920 * 1080 * 60) /* 1920 x 1080 x 60Hz */
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#define SOURCE_RESOLUTION_DETECT_TIMEOUT msecs_to_jiffies(500)
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#define RESOLUTION_CHANGE_DELAY msecs_to_jiffies(0)
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#define INVALID_RESOLUTION_DELAY msecs_to_jiffies(250)
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#define STOP_TIMEOUT msecs_to_jiffies(1000)
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#define INVALID_RESOLUTION_RETRIES 2
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#define CAPTURE_BUF_NUMBER 3 /* using how many buffers */
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#define VB_BUF_NO 0 /* there are 16 buffer, use which one */
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/* The below macros are defined for the JPEG header of the phytium JPEG Engine */
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#define PHYTIUM_JPEG_HEADER_LEN (256 * 3)
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#define PHYTIUM_JPEG_HEADER_SIZE (PHYTIUM_JPEG_HEADER_LEN / sizeof(u32))
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#define PHYTIUM_JPEG_HEADER_H_INDEX 40
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#define PHYTIUM_JPEG_HEADER_W_INDEX 41
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/* There are two ocm buffers that are used for storaging the inputing video data */
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#define OCM_BUF_NUM 2
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enum phytium_jpeg_status {
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VIDEO_MODE_DETECT_DONE,
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VIDEO_RES_CHANGE,
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VIDEO_RES_DETECT,
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VIDEO_STREAMING,
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VIDEO_FRAME_INPRG,
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VIDEO_STOPPED,
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VIDEO_CLOCKS_ON,
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VIDEO_POWEROFF,
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};
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struct phytium_jpeg_addr {
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unsigned int size;
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dma_addr_t dma_addr;
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void *virt_addr;
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};
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struct phytium_jpeg_buffer {
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struct vb2_v4l2_buffer vb;
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struct list_head link;
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};
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/**
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* struct phytium_jpeg - JPEG IP abstraction
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* @lock: the mutex protecting this structure
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* @hw_lock: spinlock protecting the hw device resource
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* @workqueue: decode work queue
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* @dev: JPEG device
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* @v4l2_dev: v4l2 device for mem2mem mode
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* @m2m_dev: v4l2 mem2mem device data
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* @alloc_ctx: videobuf2 memory allocator's context
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* @dec_vdev: video device node for decoder mem2mem mode
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* @dec_reg_base: JPEG registers mapping
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* @clk_jdec: JPEG hw working clock
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* @clk_jdec_smi: JPEG SMI bus clock
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* @larb: SMI device
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*/
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struct phytium_jpeg_dev {
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void __iomem *base_addr;
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struct device *dev;
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struct v4l2_device v4l2_dev;
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struct v4l2_pix_format pix_fmt;
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struct v4l2_bt_timings active_timings;
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struct v4l2_bt_timings detected_timings;
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u32 v4l2_input_status;
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struct vb2_queue queue;
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struct video_device vdev;
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/* v4l2 and videobuf2 lock, protect the structure*/
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struct mutex video_lock;
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u32 jpeg_mode;
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u32 comp_size_read;
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wait_queue_head_t wait;
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/* buffer list lock, protecting the hw device resource */
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spinlock_t hw_lock;
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struct delayed_work res_work;
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struct list_head buffers;
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unsigned long status;
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unsigned int sequence;
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unsigned int max_compressed_size;
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struct phytium_jpeg_addr src_addrs[OCM_BUF_NUM];
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struct phytium_jpeg_addr dst_addrs[16];
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bool yuv420;
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unsigned int frame_rate;
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void __iomem *timer30_addr;
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void __iomem *timer31_addr;
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};
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struct phytium_jpeg_config {
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u32 jpeg_mode;
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u32 comp_size_read;
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};
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#define YUV_MODE_STR_LEN 8
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#define YUVID 42
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enum jpeg_yuv_mode {
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YUV444 = 0x0,
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YUV422 = 0x1,
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YUV420 = 0x2
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};
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#endif /* _PHYTIUM_JPEG_CORE_H */
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@ -0,0 +1,113 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021-2023, Phytium Technology Co., Ltd.
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*/
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#ifndef _PHYTIUM_JPEG_REG_H
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#define _PHYTIUM_JPEG_REG_H
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#include <linux/bits.h>
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/* define the all kinds of control registers in a JPEG soc */
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/* The register is used to set the information of the video comes from main memory */
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#define SRC_DDR_INFO_REG 0x00000800
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/* The register is used to get the information of the video comes from external VGA */
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#define SRC_VGA_INFO_REG 0x00000894
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#define SRC_FORMAT BIT(0) /* 0:RGB888, 1:RGB565 */
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#define SRC_DE_POLARITY BIT(1) /* 0:low level is effect, other */
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#define SRC_HS_POLARITY BIT(2) /* 0:low level is effect, other */
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#define SRC_VS_POLARITY BIT(3) /* 0:low level is effect, other */
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#define SRC_HOR_PIXELS GENMASK(15, 4) /* the number of the horizontal pixels */
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#define SRC_WIDTH_SHIFT 4 /* shift right to get width */
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#define SRC_VER_PIXELS GENMASK(26, 16) /* the number of the vertical pixels */
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#define SRC_HEIGHT_SHIFT 16 /* shift right to get height */
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/* The below bit fields is only used by image comes from main memory */
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#define SRC_COMP_DDR_IMG_EN BIT(27) /* 0: disable to JPEG compression, others */
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/* marks which ocm buffer is occupied to store an image */
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#define SRC_DDR_IMG2OCM_VALID GENMASK(29, 28)
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/* The register controls starting work of the JPEG engine */
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#define TRANSFORM_INFO_REG 0x00000804
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#define TRANSINFO_ENABLE_ENGINE BIT(0) /* 1: enable the JPEG engine */
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/* 1: video comes from external VGA, 0: video comes from DDR */
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#define TRANSINFO_SRC_SELECT BIT(1)
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/* 0: video comes from external VGA is cached to OCM, 1: DDR */
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#define TRANSINFO_IMAGE_STORE BIT(2)
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#define TRANSINFO_FRAME_RATE GENMASK(9, 4) /* the value notes frame rate */
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#define TRANSINFO_BLOCK_SIZE BIT(12) /* 0: 8x8, 1: 16x16 */
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#define TRANSINFO_ENABLE_YUV422 BIT(13) /* 1: JPEG block is populated YUV422 */
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/* support burst with the values such as 1, 2, 4, 8, 16, 32, 64. using default value 0xf */
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#define TRANSINFO_AXI_LEN GENMASK(22, 16)
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#define TRANS_AXI_LEN_SHIFT 16
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/* The interrupt and status register */
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#define INT_STATUS_CTRL_REG 0x00000808
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#define INT_FIFO_OVERFLOW BIT(0) /* video fifo overflow, write 1 to clear */
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#define INT_OCM_BUF_OVERFLOW BIT(1) /* ocm buffer overflow, write 1 to clear */
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/* JPEG engine complete compression, write 1 to clear */
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#define INT_JPEG_ENCODE_COMPLETE BIT(2)
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/* in VGA mode, video's format is changed */
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#define INT_VIDEO_FORMAT_CHANGE BIT(3)
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/* enable the interrupt of th video fifo overflow and source resolution */
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#define DETECT_RESOLUTION_CHANGE_EN BIT(4)
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/* enable the interrupt of the ocm buffer overflow */
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#define STS_VE_OCM_BUF_OVERFLOW_EN BIT(5)
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/* enable the interrupt of the JPEG complete compression */
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#define STS_VE_JPEG_CODE_COMP_EN BIT(6)
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/* in VGA mode, the bit notes ocm buff is busy */
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#define STS_VE_OCM_BUF_BUSY BIT(7)
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/* in VGA mode, the bit notes sequence number of the frame */
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#define STS_VE_CUR_FRAME_NUMBER GENMASK(9, 8)
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/* in VGA mode, the bit notes sequence number of the cached frame */
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#define STS_VE_BUF_CACHE_NUMBER GENMASK(11, 10)
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/* in VGA mode, the buffer number in buffer list */
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#define STS_JPEG_COMP_BUF_NO GENMASK(15, 12)
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#define INT_JPEG_COMP_BUF_LIST_NO GENMASK(31, 16) /* the interrupt number of the buffer */
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#define OCM_BUF0_ADDR 0x0000080C
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#define OCM_BUF1_ADDR 0x00000810
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#define OCM_BUF_SHIFT 8
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#define BUF_LIST_BASE_ADDR 0x00000814
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#define PHYTIUM_BUF_LIST_ACTRL_AND_STS_BASE_ADDR_REG 0x00000818
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#define STS_JPEG_BUF_HIGH_LEVEL_VALID BIT(0) /* Hight levle is validity */
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#define JPEG_BUF_CAPACITY_SIZE GENMASK(29, 8) /* the capacity of the buffer */
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#define JPEG_BUF_CAPACITY_SIZE_SHIFT 8
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/* There are 16 buffers in the buffer list, the width between each other' address is 8 bytes */
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#define BUF_LIST_ADDR_OFFSET 0x8
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#define BUF_LIST_CTRL_AND_STS_OFFSET 0x8
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/* Get the address of the specific index buffer */
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#define BUF_LIST_INDEX_ADDR(index) \
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(BUF_LIST_BASE_ADDR + (index) * BUF_LIST_ADDR_OFFSET)
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#define JPEG_DST_ADDR_SHIFT 8
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#define BUF_LIST_INDEX_CTRL_STS_ADDR(index) \
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(PHYTIUM_BUF_LIST_ACTRL_AND_STS_BASE_ADDR_REG + (index) * BUF_LIST_CTRL_AND_STS_OFFSET)
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#define FRAME_SAMPLE_CTRL 0x00000898
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#define FRAME_SAMPLE_CTRL_EN BIT(31)
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#define FRAME_SAMPLE_INTERVAL GENMASK(30, 0)
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/* The below registers are all related to quantilize */
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#define HUFF_MODE_REG 0x300
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#define SAMPLE_MODE_REG 0x304
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#define Y_QUANT_BASE_ADDR_REG 0x400
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#define C_QUANT_BASE_ADDR_REG 0x500
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#define QUANT_REG_NUM 64
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#define Y_QUANT_INDEX_ADDR_REG(index) \
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(Y_QUANT_BASE_ADDR_REG + 4 * (index))
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#define C_QUANT_INDEX_ADDR_REG(index) \
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(C_QUANT_BASE_ADDR_REG + 4 * (index))
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#endif /* _PHYTIUM_JPEG_REG_H */
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