omap3 gpmc: functionality enhancement
few functions added in gpmc module and to be used by other drivers like NAND. Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Sukumar Ghorai
Tony Lindgren
parent
055a1b8c99
commit
948d38e799
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@ -46,8 +46,9 @@
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#define GPMC_ECC_CONFIG 0x1f4
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#define GPMC_ECC_CONTROL 0x1f8
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#define GPMC_ECC_SIZE_CONFIG 0x1fc
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#define GPMC_ECC1_RESULT 0x200
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#define GPMC_CS0 0x60
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#define GPMC_CS0_OFFSET 0x60
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#define GPMC_CS_SIZE 0x30
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#define GPMC_MEM_START 0x00000000
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@ -92,7 +93,8 @@ struct omap3_gpmc_regs {
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static struct resource gpmc_mem_root;
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static struct resource gpmc_cs_mem[GPMC_CS_NUM];
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static DEFINE_SPINLOCK(gpmc_mem_lock);
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static unsigned gpmc_cs_map;
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static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
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static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */
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static void __iomem *gpmc_base;
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@ -108,11 +110,27 @@ static u32 gpmc_read_reg(int idx)
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return __raw_readl(gpmc_base + idx);
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}
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static void gpmc_cs_write_byte(int cs, int idx, u8 val)
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{
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void __iomem *reg_addr;
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reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
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__raw_writeb(val, reg_addr);
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}
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static u8 gpmc_cs_read_byte(int cs, int idx)
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{
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void __iomem *reg_addr;
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reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
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return __raw_readb(reg_addr);
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}
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void gpmc_cs_write_reg(int cs, int idx, u32 val)
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{
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void __iomem *reg_addr;
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reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
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reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
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__raw_writel(val, reg_addr);
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}
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@ -120,7 +138,7 @@ u32 gpmc_cs_read_reg(int cs, int idx)
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{
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void __iomem *reg_addr;
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reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
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reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
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return __raw_readl(reg_addr);
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}
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@ -418,9 +436,158 @@ void gpmc_cs_free(int cs)
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}
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EXPORT_SYMBOL(gpmc_cs_free);
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/**
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* gpmc_read_status - read access request to get the different gpmc status
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* @cmd: command type
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* @return status
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*/
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int gpmc_read_status(int cmd)
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{
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int status = -EINVAL;
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u32 regval = 0;
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switch (cmd) {
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case GPMC_GET_IRQ_STATUS:
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status = gpmc_read_reg(GPMC_IRQSTATUS);
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break;
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case GPMC_PREFETCH_FIFO_CNT:
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regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
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status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
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break;
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case GPMC_PREFETCH_COUNT:
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regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
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status = GPMC_PREFETCH_STATUS_COUNT(regval);
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break;
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case GPMC_STATUS_BUFFER:
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regval = gpmc_read_reg(GPMC_STATUS);
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/* 1 : buffer is available to write */
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status = regval & GPMC_STATUS_BUFF_EMPTY;
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break;
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default:
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printk(KERN_ERR "gpmc_read_status: Not supported\n");
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}
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return status;
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}
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EXPORT_SYMBOL(gpmc_read_status);
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/**
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* gpmc_cs_configure - write request to configure gpmc
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* @cs: chip select number
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* @cmd: command type
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* @wval: value to write
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* @return status of the operation
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*/
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int gpmc_cs_configure(int cs, int cmd, int wval)
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{
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int err = 0;
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u32 regval = 0;
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switch (cmd) {
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case GPMC_SET_IRQ_STATUS:
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gpmc_write_reg(GPMC_IRQSTATUS, wval);
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break;
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case GPMC_CONFIG_WP:
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regval = gpmc_read_reg(GPMC_CONFIG);
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if (wval)
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regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
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else
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regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
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gpmc_write_reg(GPMC_CONFIG, regval);
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break;
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case GPMC_CONFIG_RDY_BSY:
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regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
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if (wval)
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regval |= WR_RD_PIN_MONITORING;
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else
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regval &= ~WR_RD_PIN_MONITORING;
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
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break;
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case GPMC_CONFIG_DEV_SIZE:
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regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
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regval |= GPMC_CONFIG1_DEVICESIZE(wval);
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
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break;
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case GPMC_CONFIG_DEV_TYPE:
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regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
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regval |= GPMC_CONFIG1_DEVICETYPE(wval);
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if (wval == GPMC_DEVICETYPE_NOR)
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regval |= GPMC_CONFIG1_MUXADDDATA;
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
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break;
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default:
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printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
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err = -EINVAL;
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}
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return err;
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}
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EXPORT_SYMBOL(gpmc_cs_configure);
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/**
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* gpmc_nand_read - nand specific read access request
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* @cs: chip select number
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* @cmd: command type
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*/
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int gpmc_nand_read(int cs, int cmd)
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{
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int rval = -EINVAL;
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switch (cmd) {
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case GPMC_NAND_DATA:
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rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
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break;
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default:
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printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
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}
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return rval;
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}
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EXPORT_SYMBOL(gpmc_nand_read);
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/**
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* gpmc_nand_write - nand specific write request
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* @cs: chip select number
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* @cmd: command type
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* @wval: value to write
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*/
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int gpmc_nand_write(int cs, int cmd, int wval)
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{
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int err = 0;
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switch (cmd) {
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case GPMC_NAND_COMMAND:
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gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
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break;
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case GPMC_NAND_ADDRESS:
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gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
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break;
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case GPMC_NAND_DATA:
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gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
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default:
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printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
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err = -EINVAL;
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}
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return err;
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}
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EXPORT_SYMBOL(gpmc_nand_write);
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/**
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* gpmc_prefetch_enable - configures and starts prefetch transfer
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* @cs: nand cs (chip select) number
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* @cs: cs (chip select) number
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* @dma_mode: dma mode enable (1) or disable (0)
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* @u32_count: number of bytes to be transferred
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* @is_write: prefetch read(0) or write post(1) mode
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@ -428,7 +595,6 @@ EXPORT_SYMBOL(gpmc_cs_free);
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int gpmc_prefetch_enable(int cs, int dma_mode,
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unsigned int u32_count, int is_write)
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{
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uint32_t prefetch_config1;
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if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
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/* Set the amount of bytes to be prefetched */
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@ -437,17 +603,17 @@ int gpmc_prefetch_enable(int cs, int dma_mode,
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/* Set dma/mpu mode, the prefetch read / post write and
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* enable the engine. Set which cs is has requested for.
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*/
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prefetch_config1 = ((cs << CS_NUM_SHIFT) |
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gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
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PREFETCH_FIFOTHRESHOLD |
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ENABLE_PREFETCH |
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(dma_mode << DMA_MPU_MODE) |
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(0x1 & is_write));
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gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
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(0x1 & is_write)));
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/* Start the prefetch engine */
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gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
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} else {
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return -EBUSY;
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}
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/* Start the prefetch engine */
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gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
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return 0;
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}
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@ -456,13 +622,22 @@ EXPORT_SYMBOL(gpmc_prefetch_enable);
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/**
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* gpmc_prefetch_reset - disables and stops the prefetch engine
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*/
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void gpmc_prefetch_reset(void)
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int gpmc_prefetch_reset(int cs)
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{
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u32 config1;
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/* check if the same module/cs is trying to reset */
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config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
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if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
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return -EINVAL;
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/* Stop the PFPW engine */
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gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
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/* Reset/disable the PFPW engine */
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gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
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return 0;
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}
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EXPORT_SYMBOL(gpmc_prefetch_reset);
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@ -615,3 +790,79 @@ void omap3_gpmc_restore_context(void)
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}
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}
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#endif /* CONFIG_ARCH_OMAP3 */
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/**
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* gpmc_enable_hwecc - enable hardware ecc functionality
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* @cs: chip select number
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* @mode: read/write mode
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* @dev_width: device bus width(1 for x16, 0 for x8)
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* @ecc_size: bytes for which ECC will be generated
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*/
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int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
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{
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unsigned int val;
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/* check if ecc module is in used */
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if (gpmc_ecc_used != -EINVAL)
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return -EINVAL;
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gpmc_ecc_used = cs;
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/* clear ecc and enable bits */
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val = ((0x00000001<<8) | 0x00000001);
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gpmc_write_reg(GPMC_ECC_CONTROL, val);
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/* program ecc and result sizes */
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val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
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gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
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switch (mode) {
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case GPMC_ECC_READ:
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gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
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break;
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case GPMC_ECC_READSYN:
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gpmc_write_reg(GPMC_ECC_CONTROL, 0x100);
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break;
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case GPMC_ECC_WRITE:
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gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
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break;
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default:
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printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
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break;
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}
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/* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
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val = (dev_width << 7) | (cs << 1) | (0x1);
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gpmc_write_reg(GPMC_ECC_CONFIG, val);
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return 0;
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}
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/**
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* gpmc_calculate_ecc - generate non-inverted ecc bytes
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* @cs: chip select number
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* @dat: data pointer over which ecc is computed
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* @ecc_code: ecc code buffer
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*
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* Using non-inverted ECC is considered ugly since writing a blank
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* page (padding) will clear the ECC bytes. This is not a problem as long
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* no one is trying to write data on the seemingly unused page. Reading
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* an erased page will produce an ECC mismatch between generated and read
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* ECC bytes that has to be dealt with separately.
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*/
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int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
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{
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unsigned int val = 0x0;
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if (gpmc_ecc_used != cs)
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return -EINVAL;
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/* read ecc result */
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val = gpmc_read_reg(GPMC_ECC1_RESULT);
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*ecc_code++ = val; /* P128e, ..., P1e */
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*ecc_code++ = val >> 16; /* P128o, ..., P1o */
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/* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
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*ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
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gpmc_ecc_used = -EINVAL;
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return 0;
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}
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@ -27,8 +27,27 @@
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#define GPMC_CONFIG 0x50
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#define GPMC_STATUS 0x54
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#define GPMC_CS0_BASE 0x60
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#define GPMC_CS_SIZE 0x30
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/* Control Commands */
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#define GPMC_CONFIG_RDY_BSY 0x00000001
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#define GPMC_CONFIG_DEV_SIZE 0x00000002
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#define GPMC_CONFIG_DEV_TYPE 0x00000003
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#define GPMC_SET_IRQ_STATUS 0x00000004
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#define GPMC_CONFIG_WP 0x00000005
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#define GPMC_GET_IRQ_STATUS 0x00000006
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#define GPMC_PREFETCH_FIFO_CNT 0x00000007 /* bytes available in FIFO for r/w */
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#define GPMC_PREFETCH_COUNT 0x00000008 /* remaining bytes to be read/write*/
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#define GPMC_STATUS_BUFFER 0x00000009 /* 1: buffer is available to write */
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#define GPMC_NAND_COMMAND 0x0000000a
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#define GPMC_NAND_ADDRESS 0x0000000b
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#define GPMC_NAND_DATA 0x0000000c
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/* ECC commands */
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#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
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#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
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#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
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#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
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#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
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@ -56,6 +75,14 @@
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#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
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#define GPMC_CONFIG7_CSVALID (1 << 6)
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#define GPMC_DEVICETYPE_NOR 0
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#define GPMC_DEVICETYPE_NAND 2
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#define GPMC_CONFIG_WRITEPROTECT 0x00000010
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#define GPMC_STATUS_BUFF_EMPTY 0x00000001
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#define WR_RD_PIN_MONITORING 0x00600000
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#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
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#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
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/*
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* Note that all values in this struct are in nanoseconds, while
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* the register values are in gpmc_fck cycles.
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@ -108,10 +135,16 @@ extern int gpmc_cs_set_reserved(int cs, int reserved);
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extern int gpmc_cs_reserved(int cs);
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extern int gpmc_prefetch_enable(int cs, int dma_mode,
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unsigned int u32_count, int is_write);
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extern void gpmc_prefetch_reset(void);
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extern int gpmc_prefetch_reset(int cs);
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extern int gpmc_prefetch_status(void);
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extern void omap3_gpmc_save_context(void);
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extern void omap3_gpmc_restore_context(void);
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extern void gpmc_init(void);
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extern int gpmc_read_status(int cmd);
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extern int gpmc_cs_configure(int cs, int cmd, int wval);
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extern int gpmc_nand_read(int cs, int cmd);
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extern int gpmc_nand_write(int cs, int cmd, int wval);
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int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size);
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int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code);
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#endif
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@ -319,7 +319,7 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
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} while (len);
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset();
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gpmc_prefetch_reset(info->gpmc_cs);
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}
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}
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@ -363,7 +363,7 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
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}
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset();
|
||||
gpmc_prefetch_reset(info->gpmc_cs);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue