clk: st: Support for DIVMUX and PreDiv Clocks
The patch supports the DIVMUX and PreDiv clocks used by ClockGenA(s) DIVMUX clock : Divider-Multiplexer-Gate inside ClockGenA(s) It includes support for each channel : 3-parent Multiplexer, Divider for each Parent, Gate to switch OFF the output channel. The clock is implemented using generic clocks implemented in the kernel clk_divider and clk_mux. PreDiv clock : Fixed Divider Clock used inside ClockGenA(s) to divide the oscillator clock by factor-of-16. The clock is implemented using generic clocks implemented in the kernel clk_divider. Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Gabriel FERNANDEZ
Mike Turquette
parent
c646cbf10f
commit
94885faf9d
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@ -45,6 +45,7 @@ obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/
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obj-$(CONFIG_ARCH_SIRF) += sirf/
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obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
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obj-$(CONFIG_PLAT_SPEAR) += spear/
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obj-$(CONFIG_ARCH_STI) += st/
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obj-$(CONFIG_ARCH_SUNXI) += sunxi/
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obj-$(CONFIG_ARCH_TEGRA) += tegra/
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obj-$(CONFIG_ARCH_OMAP2PLUS) += ti/
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@ -0,0 +1 @@
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obj-y += clkgen-mux.o
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@ -0,0 +1,529 @@
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/*
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* clkgen-mux.c: ST GEN-MUX Clock driver
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*
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* Copyright (C) 2014 STMicroelectronics (R&D) Limited
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*
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* Authors: Stephen Gallimore <stephen.gallimore@st.com>
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* Pankaj Dev <pankaj.dev@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/slab.h>
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#include <linux/of_address.h>
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#include <linux/clk-provider.h>
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static DEFINE_SPINLOCK(clkgena_divmux_lock);
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static const char ** __init clkgen_mux_get_parents(struct device_node *np,
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int *num_parents)
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{
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const char **parents;
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int nparents, i;
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nparents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
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if (WARN_ON(nparents <= 0))
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return ERR_PTR(-EINVAL);
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parents = kzalloc(nparents * sizeof(const char *), GFP_KERNEL);
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if (!parents)
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return ERR_PTR(-ENOMEM);
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for (i = 0; i < nparents; i++)
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parents[i] = of_clk_get_parent_name(np, i);
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*num_parents = nparents;
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return parents;
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}
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/**
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* DOC: Clock mux with a programmable divider on each of its three inputs.
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* The mux has an input setting which effectively gates its output.
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*
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* Traits of this clock:
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* prepare - clk_(un)prepare only ensures parent is (un)prepared
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* enable - clk_enable and clk_disable are functional & control gating
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* rate - set rate is supported
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* parent - set/get parent
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*/
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#define NUM_INPUTS 3
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struct clkgena_divmux {
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struct clk_hw hw;
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/* Subclassed mux and divider structures */
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struct clk_mux mux;
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struct clk_divider div[NUM_INPUTS];
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/* Enable/running feedback register bits for each input */
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void __iomem *feedback_reg[NUM_INPUTS];
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int feedback_bit_idx;
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u8 muxsel;
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};
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#define to_clkgena_divmux(_hw) container_of(_hw, struct clkgena_divmux, hw)
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struct clkgena_divmux_data {
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int num_outputs;
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int mux_offset;
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int mux_offset2;
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int mux_start_bit;
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int div_offsets[NUM_INPUTS];
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int fb_offsets[NUM_INPUTS];
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int fb_start_bit_idx;
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};
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#define CKGAX_CLKOPSRC_SWITCH_OFF 0x3
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static int clkgena_divmux_is_running(struct clkgena_divmux *mux)
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{
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u32 regval = readl(mux->feedback_reg[mux->muxsel]);
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u32 running = regval & BIT(mux->feedback_bit_idx);
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return !!running;
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}
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static int clkgena_divmux_enable(struct clk_hw *hw)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *mux_hw = &genamux->mux.hw;
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unsigned long timeout;
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int ret = 0;
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mux_hw->clk = hw->clk;
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ret = clk_mux_ops.set_parent(mux_hw, genamux->muxsel);
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if (ret)
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return ret;
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timeout = jiffies + msecs_to_jiffies(10);
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while (!clkgena_divmux_is_running(genamux)) {
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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cpu_relax();
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}
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return 0;
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}
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static void clkgena_divmux_disable(struct clk_hw *hw)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *mux_hw = &genamux->mux.hw;
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mux_hw->clk = hw->clk;
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clk_mux_ops.set_parent(mux_hw, CKGAX_CLKOPSRC_SWITCH_OFF);
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}
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static int clkgena_divmux_is_enabled(struct clk_hw *hw)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *mux_hw = &genamux->mux.hw;
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mux_hw->clk = hw->clk;
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return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
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}
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u8 clkgena_divmux_get_parent(struct clk_hw *hw)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *mux_hw = &genamux->mux.hw;
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mux_hw->clk = hw->clk;
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genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
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if ((s8)genamux->muxsel < 0) {
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pr_debug("%s: %s: Invalid parent, setting to default.\n",
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__func__, __clk_get_name(hw->clk));
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genamux->muxsel = 0;
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}
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return genamux->muxsel;
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}
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static int clkgena_divmux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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if (index >= CKGAX_CLKOPSRC_SWITCH_OFF)
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return -EINVAL;
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genamux->muxsel = index;
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/*
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* If the mux is already enabled, call enable directly to set the
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* new mux position and wait for it to start running again. Otherwise
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* do nothing.
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*/
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if (clkgena_divmux_is_enabled(hw))
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clkgena_divmux_enable(hw);
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return 0;
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}
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unsigned long clkgena_divmux_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
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div_hw->clk = hw->clk;
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return clk_divider_ops.recalc_rate(div_hw, parent_rate);
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}
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static int clkgena_divmux_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
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div_hw->clk = hw->clk;
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return clk_divider_ops.set_rate(div_hw, rate, parent_rate);
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}
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static long clkgena_divmux_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
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div_hw->clk = hw->clk;
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return clk_divider_ops.round_rate(div_hw, rate, prate);
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}
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static const struct clk_ops clkgena_divmux_ops = {
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.enable = clkgena_divmux_enable,
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.disable = clkgena_divmux_disable,
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.is_enabled = clkgena_divmux_is_enabled,
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.get_parent = clkgena_divmux_get_parent,
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.set_parent = clkgena_divmux_set_parent,
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.round_rate = clkgena_divmux_round_rate,
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.recalc_rate = clkgena_divmux_recalc_rate,
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.set_rate = clkgena_divmux_set_rate,
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};
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/**
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* clk_register_genamux - register a genamux clock with the clock framework
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*/
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struct clk *clk_register_genamux(const char *name,
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const char **parent_names, u8 num_parents,
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void __iomem *reg,
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const struct clkgena_divmux_data *muxdata,
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u32 idx)
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{
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/*
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* Fixed constants across all ClockgenA variants
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*/
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const int mux_width = 2;
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const int divider_width = 5;
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struct clkgena_divmux *genamux;
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struct clk *clk;
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struct clk_init_data init;
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int i;
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genamux = kzalloc(sizeof(*genamux), GFP_KERNEL);
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if (!genamux)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clkgena_divmux_ops;
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init.flags = CLK_IS_BASIC;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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genamux->mux.lock = &clkgena_divmux_lock;
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genamux->mux.mask = BIT(mux_width) - 1;
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genamux->mux.shift = muxdata->mux_start_bit + (idx * mux_width);
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if (genamux->mux.shift > 31) {
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/*
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* We have spilled into the second mux register so
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* adjust the register address and the bit shift accordingly
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*/
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genamux->mux.reg = reg + muxdata->mux_offset2;
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genamux->mux.shift -= 32;
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} else {
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genamux->mux.reg = reg + muxdata->mux_offset;
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}
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for (i = 0; i < NUM_INPUTS; i++) {
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/*
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* Divider config for each input
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*/
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void __iomem *divbase = reg + muxdata->div_offsets[i];
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genamux->div[i].width = divider_width;
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genamux->div[i].reg = divbase + (idx * sizeof(u32));
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/*
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* Mux enabled/running feedback register for each input.
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*/
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genamux->feedback_reg[i] = reg + muxdata->fb_offsets[i];
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}
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genamux->feedback_bit_idx = muxdata->fb_start_bit_idx + idx;
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genamux->hw.init = &init;
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clk = clk_register(NULL, &genamux->hw);
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if (IS_ERR(clk)) {
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kfree(genamux);
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goto err;
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}
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pr_debug("%s: parent %s rate %lu\n",
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__clk_get_name(clk),
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__clk_get_name(clk_get_parent(clk)),
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clk_get_rate(clk));
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err:
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return clk;
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}
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static struct clkgena_divmux_data st_divmux_c65hs = {
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.num_outputs = 4,
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.mux_offset = 0x14,
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.mux_start_bit = 0,
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.div_offsets = { 0x800, 0x900, 0xb00 },
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.fb_offsets = { 0x18, 0x1c, 0x20 },
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.fb_start_bit_idx = 0,
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};
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static struct clkgena_divmux_data st_divmux_c65ls = {
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.num_outputs = 14,
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.mux_offset = 0x14,
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.mux_offset2 = 0x24,
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.mux_start_bit = 8,
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.div_offsets = { 0x810, 0xa10, 0xb10 },
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.fb_offsets = { 0x18, 0x1c, 0x20 },
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.fb_start_bit_idx = 4,
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};
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static struct clkgena_divmux_data st_divmux_c32odf0 = {
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.num_outputs = 8,
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.mux_offset = 0x1c,
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.mux_start_bit = 0,
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.div_offsets = { 0x800, 0x900, 0xa60 },
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.fb_offsets = { 0x2c, 0x24, 0x28 },
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.fb_start_bit_idx = 0,
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};
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static struct clkgena_divmux_data st_divmux_c32odf1 = {
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.num_outputs = 8,
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.mux_offset = 0x1c,
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.mux_start_bit = 16,
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.div_offsets = { 0x820, 0x980, 0xa80 },
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.fb_offsets = { 0x2c, 0x24, 0x28 },
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.fb_start_bit_idx = 8,
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};
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static struct clkgena_divmux_data st_divmux_c32odf2 = {
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.num_outputs = 8,
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.mux_offset = 0x20,
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.mux_start_bit = 0,
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.div_offsets = { 0x840, 0xa20, 0xb10 },
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.fb_offsets = { 0x2c, 0x24, 0x28 },
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.fb_start_bit_idx = 16,
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};
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static struct clkgena_divmux_data st_divmux_c32odf3 = {
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.num_outputs = 8,
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.mux_offset = 0x20,
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.mux_start_bit = 16,
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.div_offsets = { 0x860, 0xa40, 0xb30 },
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.fb_offsets = { 0x2c, 0x24, 0x28 },
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.fb_start_bit_idx = 24,
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};
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static struct of_device_id clkgena_divmux_of_match[] = {
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{
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.compatible = "st,clkgena-divmux-c65-hs",
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.data = &st_divmux_c65hs,
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},
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{
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.compatible = "st,clkgena-divmux-c65-ls",
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.data = &st_divmux_c65ls,
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},
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{
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.compatible = "st,clkgena-divmux-c32-odf0",
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.data = &st_divmux_c32odf0,
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},
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{
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.compatible = "st,clkgena-divmux-c32-odf1",
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.data = &st_divmux_c32odf1,
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},
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{
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.compatible = "st,clkgena-divmux-c32-odf2",
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.data = &st_divmux_c32odf2,
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},
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{
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.compatible = "st,clkgena-divmux-c32-odf3",
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.data = &st_divmux_c32odf3,
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},
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{}
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};
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static void __iomem * __init clkgen_get_register_base(
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struct device_node *np)
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{
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struct device_node *pnode;
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void __iomem *reg = NULL;
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pnode = of_get_parent(np);
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if (!pnode)
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return NULL;
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reg = of_iomap(pnode, 0);
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of_node_put(pnode);
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return reg;
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}
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void __init st_of_clkgena_divmux_setup(struct device_node *np)
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{
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const struct of_device_id *match;
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const struct clkgena_divmux_data *data;
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struct clk_onecell_data *clk_data;
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void __iomem *reg;
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const char **parents;
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int num_parents = 0, i;
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match = of_match_node(clkgena_divmux_of_match, np);
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if (WARN_ON(!match))
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return;
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data = (struct clkgena_divmux_data *)match->data;
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reg = clkgen_get_register_base(np);
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if (!reg)
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return;
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parents = clkgen_mux_get_parents(np, &num_parents);
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if (IS_ERR(parents))
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return;
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clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
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if (!clk_data)
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goto err;
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clk_data->clk_num = data->num_outputs;
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clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *),
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GFP_KERNEL);
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if (!clk_data->clks)
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goto err;
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for (i = 0; i < clk_data->clk_num; i++) {
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struct clk *clk;
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const char *clk_name;
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if (of_property_read_string_index(np, "clock-output-names",
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i, &clk_name))
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break;
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/*
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* If we read an empty clock name then the output is unused
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*/
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if (*clk_name == '\0')
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continue;
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clk = clk_register_genamux(clk_name, parents, num_parents,
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reg, data, i);
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if (IS_ERR(clk))
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goto err;
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clk_data->clks[i] = clk;
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}
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kfree(parents);
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of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
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return;
|
||||
err:
|
||||
if (clk_data)
|
||||
kfree(clk_data->clks);
|
||||
|
||||
kfree(clk_data);
|
||||
kfree(parents);
|
||||
}
|
||||
CLK_OF_DECLARE(clkgenadivmux, "st,clkgena-divmux", st_of_clkgena_divmux_setup);
|
||||
|
||||
struct clkgena_prediv_data {
|
||||
u32 offset;
|
||||
u8 shift;
|
||||
struct clk_div_table *table;
|
||||
};
|
||||
|
||||
static struct clk_div_table prediv_table16[] = {
|
||||
{ .val = 0, .div = 1 },
|
||||
{ .val = 1, .div = 16 },
|
||||
{ .div = 0 },
|
||||
};
|
||||
|
||||
static struct clkgena_prediv_data prediv_c65_data = {
|
||||
.offset = 0x4c,
|
||||
.shift = 31,
|
||||
.table = prediv_table16,
|
||||
};
|
||||
|
||||
static struct clkgena_prediv_data prediv_c32_data = {
|
||||
.offset = 0x50,
|
||||
.shift = 1,
|
||||
.table = prediv_table16,
|
||||
};
|
||||
|
||||
static struct of_device_id clkgena_prediv_of_match[] = {
|
||||
{ .compatible = "st,clkgena-prediv-c65", .data = &prediv_c65_data },
|
||||
{ .compatible = "st,clkgena-prediv-c32", .data = &prediv_c32_data },
|
||||
{}
|
||||
};
|
||||
|
||||
void __init st_of_clkgena_prediv_setup(struct device_node *np)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
void __iomem *reg;
|
||||
const char *parent_name, *clk_name;
|
||||
struct clk *clk;
|
||||
struct clkgena_prediv_data *data;
|
||||
|
||||
match = of_match_node(clkgena_prediv_of_match, np);
|
||||
if (!match) {
|
||||
pr_err("%s: No matching data\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
data = (struct clkgena_prediv_data *)match->data;
|
||||
|
||||
reg = clkgen_get_register_base(np);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
if (!parent_name)
|
||||
return;
|
||||
|
||||
if (of_property_read_string_index(np, "clock-output-names",
|
||||
0, &clk_name))
|
||||
return;
|
||||
|
||||
clk = clk_register_divider_table(NULL, clk_name, parent_name, 0,
|
||||
reg + data->offset, data->shift, 1,
|
||||
0, data->table, NULL);
|
||||
if (IS_ERR(clk))
|
||||
return;
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
pr_debug("%s: parent %s rate %u\n",
|
||||
__clk_get_name(clk),
|
||||
__clk_get_name(clk_get_parent(clk)),
|
||||
(unsigned int)clk_get_rate(clk));
|
||||
|
||||
return;
|
||||
}
|
||||
CLK_OF_DECLARE(clkgenaprediv, "st,clkgena-prediv", st_of_clkgena_prediv_setup);
|
||||
Loading…
Reference in New Issue