ufs: add support for Synopsys G210 Test Chip
This patch adds support for Synopsys G210 Test Chip. Signed-off-by: Joao Pinto <jpinto@synopsys.com> Reviewed-by: Hannes Reinicke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Joao Pinto
Martin K. Petersen
parent
4b9ffb5a35
commit
947e7013c7
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/*
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* Synopsys G210 Test Chip driver
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*
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* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
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*
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* Authors: Joao Pinto <jpinto@synopsys.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "ufshcd.h"
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#include "unipro.h"
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#include "ufshcd-dwc.h"
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#include "ufshci-dwc.h"
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/**
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* tc_dwc_g210_setup_40bit_rmmi()
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* This function configures Synopsys TC specific atributes (40-bit RMMI)
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* @hba: Pointer to drivers structure
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*
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* Returns 0 on success or non-zero value on failure
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*/
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static int tc_dwc_g210_setup_40bit_rmmi(struct ufs_hba *hba)
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{
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const struct ufshcd_dme_attr_val setup_attrs[] = {
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{ UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },
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{ UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },
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{ UIC_ARG_MIB(CDIRECTCTRL6), 0x80, DME_LOCAL },
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{ UIC_ARG_MIB(CBDIVFACTOR), 0x08, DME_LOCAL },
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{ UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },
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{ UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },
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{ UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },
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{ UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x14,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 4,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,
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DME_LOCAL },
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{ UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },
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{ UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,
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DME_LOCAL },
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{ UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },
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};
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return ufshcd_dwc_dme_set_attrs(hba, setup_attrs,
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ARRAY_SIZE(setup_attrs));
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}
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/**
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* tc_dwc_g210_setup_20bit_rmmi_lane0()
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* This function configures Synopsys TC 20-bit RMMI Lane 0
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* @hba: Pointer to drivers structure
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*
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* Returns 0 on success or non-zero value on failure
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*/
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static int tc_dwc_g210_setup_20bit_rmmi_lane0(struct ufs_hba *hba)
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{
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const struct ufshcd_dme_attr_val setup_attrs[] = {
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{ UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x12,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 2,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,
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DME_LOCAL },
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{ UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },
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{ UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },
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{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,
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DME_LOCAL },
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{ UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },
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};
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return ufshcd_dwc_dme_set_attrs(hba, setup_attrs,
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ARRAY_SIZE(setup_attrs));
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}
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/**
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* tc_dwc_g210_setup_20bit_rmmi_lane1()
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* This function configures Synopsys TC 20-bit RMMI Lane 1
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* @hba: Pointer to drivers structure
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*
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* Returns 0 on success or non-zero value on failure
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*/
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static int tc_dwc_g210_setup_20bit_rmmi_lane1(struct ufs_hba *hba)
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{
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int connected_rx_lanes = 0;
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int connected_tx_lanes = 0;
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int ret = 0;
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const struct ufshcd_dme_attr_val setup_tx_attrs[] = {
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{ UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN1_TX), 0x0d,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN1_TX), 0x19,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN1_TX), 0x12,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,
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DME_LOCAL },
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};
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const struct ufshcd_dme_attr_val setup_rx_attrs[] = {
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{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN1_RX), 0x01,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN1_RX), 0x19,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN1_RX), 2,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN1_RX), 0x80,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN1_RX), 0x03,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN1_RX), 0x16,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN1_RX), 0x42,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN1_RX), 0xa4,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN1_RX), 0x01,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN1_RX), 0x01,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN1_RX), 0x28,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN1_RX), 0x1E,
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DME_LOCAL },
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{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN1_RX), 0x2f,
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DME_LOCAL },
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};
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/* Get the available lane count */
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ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
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&connected_rx_lanes);
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ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
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&connected_tx_lanes);
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if (connected_tx_lanes == 2) {
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ret = ufshcd_dwc_dme_set_attrs(hba, setup_tx_attrs,
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ARRAY_SIZE(setup_tx_attrs));
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if (ret)
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goto out;
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}
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if (connected_rx_lanes == 2) {
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ret = ufshcd_dwc_dme_set_attrs(hba, setup_rx_attrs,
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ARRAY_SIZE(setup_rx_attrs));
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}
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out:
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return ret;
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}
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/**
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* tc_dwc_g210_setup_20bit_rmmi()
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* This function configures Synopsys TC specific atributes (20-bit RMMI)
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* @hba: Pointer to drivers structure
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*
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* Returns 0 on success or non-zero value on failure
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*/
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static int tc_dwc_g210_setup_20bit_rmmi(struct ufs_hba *hba)
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{
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int ret = 0;
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const struct ufshcd_dme_attr_val setup_attrs[] = {
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{ UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },
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{ UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },
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{ UIC_ARG_MIB(CDIRECTCTRL6), 0xc0, DME_LOCAL },
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{ UIC_ARG_MIB(CBDIVFACTOR), 0x44, DME_LOCAL },
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{ UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },
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{ UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },
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{ UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },
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};
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ret = ufshcd_dwc_dme_set_attrs(hba, setup_attrs,
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ARRAY_SIZE(setup_attrs));
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if (ret)
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goto out;
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/* Lane 0 configuration*/
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ret = tc_dwc_g210_setup_20bit_rmmi_lane0(hba);
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if (ret)
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goto out;
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/* Lane 1 configuration*/
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ret = tc_dwc_g210_setup_20bit_rmmi_lane1(hba);
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if (ret)
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goto out;
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out:
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return ret;
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}
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/**
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* tc_dwc_g210_config_40_bit()
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* This function configures Local (host) Synopsys 40-bit TC specific attributes
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*
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* @hba: Pointer to drivers structure
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*
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* Returns 0 on success non-zero value on failure
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*/
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int tc_dwc_g210_config_40_bit(struct ufs_hba *hba)
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{
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int ret = 0;
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dev_info(hba->dev, "Configuring Test Chip 40-bit RMMI\n");
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ret = tc_dwc_g210_setup_40bit_rmmi(hba);
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if (ret) {
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dev_err(hba->dev, "Configuration failed\n");
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goto out;
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}
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/* To write Shadow register bank to effective configuration block */
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
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if (ret)
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goto out;
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/* To configure Debug OMC */
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);
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out:
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return ret;
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}
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EXPORT_SYMBOL(tc_dwc_g210_config_40_bit);
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/**
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* tc_dwc_g210_config_20_bit()
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* This function configures Local (host) Synopsys 20-bit TC specific attributes
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*
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* @hba: Pointer to drivers structure
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*
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* Returns 0 on success non-zero value on failure
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*/
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int tc_dwc_g210_config_20_bit(struct ufs_hba *hba)
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{
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int ret = 0;
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dev_info(hba->dev, "Configuring Test Chip 20-bit RMMI\n");
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ret = tc_dwc_g210_setup_20bit_rmmi(hba);
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if (ret) {
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dev_err(hba->dev, "Configuration failed\n");
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goto out;
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}
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/* To write Shadow register bank to effective configuration block */
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
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if (ret)
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goto out;
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/* To configure Debug OMC */
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);
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out:
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return ret;
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}
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EXPORT_SYMBOL(tc_dwc_g210_config_20_bit);
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@ -0,0 +1,19 @@
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/*
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* Synopsys G210 Test Chip driver
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*
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* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
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*
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* Authors: Joao Pinto <jpinto@synopsys.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _TC_DWC_G210_H
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#define _TC_DWC_G210_H
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int tc_dwc_g210_config_40_bit(struct ufs_hba *hba);
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int tc_dwc_g210_config_20_bit(struct ufs_hba *hba);
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#endif /* End of Header */
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