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Merge branch 'ixp4xx' of git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux-2.6 

* 'ixp4xx' of git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux-2.6:
  IXP4xx: Fix LL debugging on little-endian CPU.
  IXP4xx: Fix sparse warnings in I/O primitives.
  IXP4xx: Make mdio_bus struct static in the Ethernet driver.
  IXP4xx: Fix ixp4xx_crypto little-endian operation.
  IXP4xx: Prevent HSS transmitter lockup by disabling FRaMe signals.
  ixp4xx/vulcan: add PCI support
  ixp4xx: base support for Arcom Vulcan
This commit is contained in:
Linus Torvalds 2010-08-11 09:17:27 -07:00
parent 636d17427b 42ea573f87
commit 946880fa27
9 changed files with 357 additions and 5 deletions
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8
arch/arm/mach-ixp4xx/Kconfig
View File

@ -140,6 +140,14 @@ config MACH_FSG
FSG-3 device. For more information on this platform,
see http://www.nslu2-linux.org/wiki/FSG3/HomePage
config MACH_ARCOM_VULCAN
bool
prompt "Arcom/Eurotech Vulcan"
select PCI
help
Say 'Y' here if you want your kernel to support Arcom's
Vulcan board.
#
# Certain registers and IRQs are only enabled if supporting IXP465 CPUs
#

2
arch/arm/mach-ixp4xx/Makefile
View File

@ -16,6 +16,7 @@ obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o
obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-pci.o
obj-y += common.o
@ -31,6 +32,7 @@ obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
obj-$(CONFIG_MACH_FSG) += fsg-setup.o
obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o
obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-setup.o
obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o

2
arch/arm/mach-ixp4xx/include/mach/debug-macro.S
View File

@ -16,8 +16,10 @@
moveq \rx, #0xc8000000
movne \rx, #0xff000000
orrne \rx, \rx, #0x00b00000
#ifdef __ARMEB__
add \rx,\rx,#3 @ Uart regs are at off set of 3 if
@ byte writes used - Big Endian.
#endif
.endm
#define UART_SHIFT 2

6
arch/arm/mach-ixp4xx/include/mach/io.h
View File

@ -353,7 +353,7 @@ static inline unsigned int ioread8(const void __iomem *addr)
return (unsigned int)inb(port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return (unsigned int)__raw_readb(port);
return (unsigned int)__raw_readb(addr);
#else
return (unsigned int)__indirect_readb(addr);
#endif
@ -381,7 +381,7 @@ static inline unsigned int ioread16(const void __iomem *addr)
return (unsigned int)inw(port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return le16_to_cpu(__raw_readw((u32)port));
return le16_to_cpu((__force __le16)__raw_readw(addr));
#else
return (unsigned int)__indirect_readw(addr);
#endif
@ -440,7 +440,7 @@ static inline void iowrite8(u8 value, void __iomem *addr)
outb(value, port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writeb(value, port);
__raw_writeb(value, addr);
#else
__indirect_writeb(value, addr);
#endif

73
arch/arm/mach-ixp4xx/vulcan-pci.c Normal file
View File

@ -0,0 +1,73 @@
/*
* arch/arch/mach-ixp4xx/vulcan-pci.c
*
* Vulcan board-level PCI initialization
*
* Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
*
* based on ixdp425-pci.c:
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 2
#define INTB 3
void __init vulcan_pci_preinit(void)
{
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
/*
* Cardbus bridge wants way more than the SoC can actually offer,
* and leaves the whole PCI bus in a mess. Artificially limit it
* to 8MB per region. Of course indirect mode doesn't have this
* limitation...
*/
pci_cardbus_mem_size = SZ_8M;
pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
(int)(pci_cardbus_mem_size >> 20));
#endif
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init vulcan_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot == 1)
return IXP4XX_GPIO_IRQ(INTA);
if (slot == 2)
return IXP4XX_GPIO_IRQ(INTB);
return -1;
}
struct hw_pci vulcan_pci __initdata = {
.nr_controllers = 1,
.preinit = vulcan_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = vulcan_map_irq,
};
int __init vulcan_pci_init(void)
{
if (machine_is_arcom_vulcan())
pci_common_init(&vulcan_pci);
return 0;
}
subsys_initcall(vulcan_pci_init);

246
arch/arm/mach-ixp4xx/vulcan-setup.c Normal file
View File

@ -0,0 +1,246 @@
/*
* arch/arm/mach-ixp4xx/vulcan-setup.c
*
* Arcom/Eurotech Vulcan board-setup
*
* Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
*
* based on fsg-setup.c:
* Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
*/
#include <linux/if_ether.h>
#include <linux/irq.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/io.h>
#include <linux/w1-gpio.h>
#include <linux/mtd/plat-ram.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
static struct flash_platform_data vulcan_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource vulcan_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device vulcan_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &vulcan_flash_data,
},
.resource = &vulcan_flash_resource,
.num_resources = 1,
};
static struct platdata_mtd_ram vulcan_sram_data = {
.mapname = "Vulcan SRAM",
.bankwidth = 1,
};
static struct resource vulcan_sram_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device vulcan_sram = {
.name = "mtd-ram",
.id = 0,
.dev = {
.platform_data = &vulcan_sram_data,
},
.resource = &vulcan_sram_resource,
.num_resources = 1,
};
static struct resource vulcan_uart_resources[] = {
[0] = {
.start = IXP4XX_UART1_BASE_PHYS,
.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
[2] = {
.flags = IORESOURCE_MEM,
},
};
static struct plat_serial8250_port vulcan_uart_data[] = {
[0] = {
.mapbase = IXP4XX_UART1_BASE_PHYS,
.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART1,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
[1] = {
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
[2] = {
.irq = IXP4XX_GPIO_IRQ(4),
.irqflags = IRQF_TRIGGER_LOW,
.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.uartclk = 1843200,
},
[3] = {
.irq = IXP4XX_GPIO_IRQ(4),
.irqflags = IRQF_TRIGGER_LOW,
.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.uartclk = 1843200,
},
{ }
};
static struct platform_device vulcan_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = vulcan_uart_data,
},
.resource = vulcan_uart_resources,
.num_resources = ARRAY_SIZE(vulcan_uart_resources),
};
static struct eth_plat_info vulcan_plat_eth[] = {
[0] = {
.phy = 0,
.rxq = 3,
.txreadyq = 20,
},
[1] = {
.phy = 1,
.rxq = 4,
.txreadyq = 21,
},
};
static struct platform_device vulcan_eth[] = {
[0] = {
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEB,
.dev = {
.platform_data = &vulcan_plat_eth[0],
},
},
[1] = {
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEC,
.dev = {
.platform_data = &vulcan_plat_eth[1],
},
},
};
static struct resource vulcan_max6369_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device vulcan_max6369 = {
.name = "max6369_wdt",
.id = -1,
.resource = &vulcan_max6369_resource,
.num_resources = 1,
};
static struct w1_gpio_platform_data vulcan_w1_gpio_pdata = {
.pin = 14,
};
static struct platform_device vulcan_w1_gpio = {
.name = "w1-gpio",
.id = 0,
.dev = {
.platform_data = &vulcan_w1_gpio_pdata,
},
};
static struct platform_device *vulcan_devices[] __initdata = {
&vulcan_uart,
&vulcan_flash,
&vulcan_sram,
&vulcan_max6369,
&vulcan_eth[0],
&vulcan_eth[1],
&vulcan_w1_gpio,
};
static void __init vulcan_init(void)
{
ixp4xx_sys_init();
/* Flash is spread over both CS0 and CS1 */
vulcan_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
vulcan_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
*IXP4XX_EXP_CS0 = IXP4XX_EXP_BUS_CS_EN |
IXP4XX_EXP_BUS_STROBE_T(3) |
IXP4XX_EXP_BUS_SIZE(0xF) |
IXP4XX_EXP_BUS_BYTE_RD16 |
IXP4XX_EXP_BUS_WR_EN;
*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
/* SRAM on CS2, (256kB, 8bit, writable) */
vulcan_sram_resource.start = IXP4XX_EXP_BUS_BASE(2);
vulcan_sram_resource.end = IXP4XX_EXP_BUS_BASE(2) + SZ_256K - 1;
*IXP4XX_EXP_CS2 = IXP4XX_EXP_BUS_CS_EN |
IXP4XX_EXP_BUS_STROBE_T(1) |
IXP4XX_EXP_BUS_HOLD_T(2) |
IXP4XX_EXP_BUS_SIZE(9) |
IXP4XX_EXP_BUS_SPLT_EN |
IXP4XX_EXP_BUS_WR_EN |
IXP4XX_EXP_BUS_BYTE_EN;
/* XR16L2551 on CS3 (Moto style, 512 bytes, 8bits, writable) */
vulcan_uart_resources[2].start = IXP4XX_EXP_BUS_BASE(3);
vulcan_uart_resources[2].end = IXP4XX_EXP_BUS_BASE(3) + 16 - 1;
vulcan_uart_data[2].mapbase = vulcan_uart_resources[2].start;
vulcan_uart_data[3].mapbase = vulcan_uart_data[2].mapbase + 8;
*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
IXP4XX_EXP_BUS_STROBE_T(3) |
IXP4XX_EXP_BUS_CYCLES(IXP4XX_EXP_BUS_CYCLES_MOTOROLA)|
IXP4XX_EXP_BUS_WR_EN |
IXP4XX_EXP_BUS_BYTE_EN;
/* GPIOS on CS4 (512 bytes, 8bits, writable) */
*IXP4XX_EXP_CS4 = IXP4XX_EXP_BUS_CS_EN |
IXP4XX_EXP_BUS_WR_EN |
IXP4XX_EXP_BUS_BYTE_EN;
/* max6369 on CS5 (512 bytes, 8bits, writable) */
vulcan_max6369_resource.start = IXP4XX_EXP_BUS_BASE(5);
vulcan_max6369_resource.end = IXP4XX_EXP_BUS_BASE(5);
*IXP4XX_EXP_CS5 = IXP4XX_EXP_BUS_CS_EN |
IXP4XX_EXP_BUS_WR_EN |
IXP4XX_EXP_BUS_BYTE_EN;
platform_add_devices(vulcan_devices, ARRAY_SIZE(vulcan_devices));
}
MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
/* Maintainer: Marc Zyngier <maz@misterjones.org> */
.phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
.io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
.map_io = ixp4xx_map_io,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.boot_params = 0x0100,
.init_machine = vulcan_init,
MACHINE_END

21
drivers/crypto/ixp4xx_crypto.c
View File

@ -97,8 +97,13 @@
struct buffer_desc {
u32 phys_next;
#ifdef __ARMEB__
u16 buf_len;
u16 pkt_len;
#else
u16 pkt_len;
u16 buf_len;
#endif
u32 phys_addr;
u32 __reserved[4];
struct buffer_desc *next;
@ -106,17 +111,30 @@ struct buffer_desc {
};
struct crypt_ctl {
#ifdef __ARMEB__
u8 mode; /* NPE_OP_* operation mode */
u8 init_len;
u16 reserved;
#else
u16 reserved;
u8 init_len;
u8 mode; /* NPE_OP_* operation mode */
#endif
u8 iv[MAX_IVLEN]; /* IV for CBC mode or CTR IV for CTR mode */
u32 icv_rev_aes; /* icv or rev aes */
u32 src_buf;
u32 dst_buf;
#ifdef __ARMEB__
u16 auth_offs; /* Authentication start offset */
u16 auth_len; /* Authentication data length */
u16 crypt_offs; /* Cryption start offset */
u16 crypt_len; /* Cryption data length */
#else
u16 auth_len; /* Authentication data length */
u16 auth_offs; /* Authentication start offset */
u16 crypt_len; /* Cryption data length */
u16 crypt_offs; /* Cryption start offset */
#endif
u32 aadAddr; /* Additional Auth Data Addr for CCM mode */
u32 crypto_ctx; /* NPE Crypto Param structure address */
@ -652,6 +670,9 @@ static int setup_auth(struct crypto_tfm *tfm, int encrypt, unsigned authsize,
/* write cfg word to cryptinfo */
cfgword = algo->cfgword | ( authsize << 6); /* (authsize/4) << 8 */
#ifndef __ARMEB__
cfgword ^= 0xAA000000; /* change the "byte swap" flags */
#endif
*(u32*)cinfo = cpu_to_be32(cfgword);
cinfo += sizeof(cfgword);

2
drivers/net/arm/ixp4xx_eth.c
View File

@ -241,7 +241,7 @@ static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
static spinlock_t mdio_lock;
static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
struct mii_bus *mdio_bus;
static struct mii_bus *mdio_bus;
static int ports_open;
static struct port *npe_port_tab[MAX_NPES];
static struct dma_pool *dma_pool;

2
drivers/net/wan/ixp4xx_hss.c
View File

@ -396,7 +396,7 @@ static void hss_config(struct port *port)
msg.cmd = PORT_CONFIG_WRITE;
msg.hss_port = port->id;
msg.index = HSS_CONFIG_TX_PCR;
msg.data32 = PCR_FRM_SYNC_OUTPUT_RISING | PCR_MSB_ENDIAN |
msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |
PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
if (port->clock_type == CLOCK_INT)
msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;