iio: adis16480: support burst read function
Some supported devices support burst read function. This provides a method for reading a batch of data (status, temperature, gyroscopes, accelerometers, time stamp/data counter, and CRC code), which does not require a stall time between each 16-bit segment and only requires one command on the DIN line to initiate. Devices supporting this mode are: * adis16495-1 * adis16495-2 * adis16495-3 * adis16497-1 * adis16497-2 * adis16497-3 Reviewed-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Nuno Sa <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20210422103735.136367-1-nuno.sa@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Nuno Sa
Jonathan Cameron
parent
e50f8e0495
commit
941f130881
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@ -19,11 +19,15 @@
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#include <linux/sysfs.h>
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#include <linux/module.h>
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#include <linux/lcm.h>
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#include <linux/swab.h>
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#include <linux/crc32.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/imu/adis.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/debugfs.h>
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@ -103,6 +107,12 @@
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* Available only for ADIS1649x devices
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*/
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#define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10)
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#define ADIS16495_REG_BURST_CMD ADIS16480_REG(0x00, 0x7C)
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#define ADIS16495_BURST_ID 0xA5A5
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/* total number of segments in burst */
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#define ADIS16495_BURST_MAX_DATA 20
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/* spi max speed in burst mode */
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#define ADIS16495_BURST_MAX_SPEED 6000000
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#define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20)
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@ -163,6 +173,8 @@ struct adis16480 {
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struct clk *ext_clk;
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enum adis16480_clock_mode clk_mode;
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unsigned int clk_freq;
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/* Alignment needed for the timestamp */
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__be16 data[ADIS16495_BURST_MAX_DATA] __aligned(8);
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};
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static const char * const adis16480_int_pin_names[4] = {
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@ -863,7 +875,7 @@ static const char * const adis16480_status_error_msgs[] = {
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static int adis16480_enable_irq(struct adis *adis, bool enable);
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#define ADIS16480_DATA(_prod_id, _timeouts) \
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#define ADIS16480_DATA(_prod_id, _timeouts, _burst_len) \
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{ \
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.diag_stat_reg = ADIS16480_REG_DIAG_STS, \
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.glob_cmd_reg = ADIS16480_REG_GLOB_CMD, \
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@ -887,6 +899,9 @@ static int adis16480_enable_irq(struct adis *adis, bool enable);
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BIT(ADIS16480_DIAG_STAT_BARO_FAIL), \
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.enable_irq = adis16480_enable_irq, \
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.timeouts = (_timeouts), \
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.burst_reg_cmd = ADIS16495_REG_BURST_CMD, \
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.burst_len = (_burst_len), \
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.burst_max_speed_hz = ADIS16495_BURST_MAX_SPEED \
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}
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static const struct adis_timeout adis16485_timeouts = {
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@ -931,7 +946,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = {
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.int_clk = 2460000,
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.max_dec_rate = 2048,
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.filter_freqs = adis16480_def_filter_freqs,
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.adis_data = ADIS16480_DATA(16375, &adis16485_timeouts),
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.adis_data = ADIS16480_DATA(16375, &adis16485_timeouts, 0),
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},
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[ADIS16480] = {
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.channels = adis16480_channels,
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@ -944,7 +959,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = {
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.int_clk = 2460000,
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.max_dec_rate = 2048,
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.filter_freqs = adis16480_def_filter_freqs,
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.adis_data = ADIS16480_DATA(16480, &adis16480_timeouts),
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.adis_data = ADIS16480_DATA(16480, &adis16480_timeouts, 0),
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},
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[ADIS16485] = {
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.channels = adis16485_channels,
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@ -957,7 +972,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = {
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.int_clk = 2460000,
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.max_dec_rate = 2048,
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.filter_freqs = adis16480_def_filter_freqs,
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.adis_data = ADIS16480_DATA(16485, &adis16485_timeouts),
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.adis_data = ADIS16480_DATA(16485, &adis16485_timeouts, 0),
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},
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[ADIS16488] = {
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.channels = adis16480_channels,
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@ -970,7 +985,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = {
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.int_clk = 2460000,
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.max_dec_rate = 2048,
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.filter_freqs = adis16480_def_filter_freqs,
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.adis_data = ADIS16480_DATA(16488, &adis16485_timeouts),
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.adis_data = ADIS16480_DATA(16488, &adis16485_timeouts, 0),
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},
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[ADIS16490] = {
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.channels = adis16485_channels,
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@ -984,7 +999,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = {
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.max_dec_rate = 4250,
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.filter_freqs = adis16495_def_filter_freqs,
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.has_pps_clk_mode = true,
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.adis_data = ADIS16480_DATA(16490, &adis16495_timeouts),
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.adis_data = ADIS16480_DATA(16490, &adis16495_timeouts, 0),
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},
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[ADIS16495_1] = {
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.channels = adis16485_channels,
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@ -998,7 +1013,9 @@ static const struct adis16480_chip_info adis16480_chip_info[] = {
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.max_dec_rate = 4250,
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.filter_freqs = adis16495_def_filter_freqs,
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.has_pps_clk_mode = true,
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.adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts),
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/* 20 elements of 16bits */
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.adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
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ADIS16495_BURST_MAX_DATA * 2),
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},
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[ADIS16495_2] = {
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.channels = adis16485_channels,
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@ -1012,7 +1029,9 @@ static const struct adis16480_chip_info adis16480_chip_info[] = {
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.max_dec_rate = 4250,
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.filter_freqs = adis16495_def_filter_freqs,
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.has_pps_clk_mode = true,
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.adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts),
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/* 20 elements of 16bits */
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.adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
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ADIS16495_BURST_MAX_DATA * 2),
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},
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[ADIS16495_3] = {
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.channels = adis16485_channels,
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@ -1026,7 +1045,9 @@ static const struct adis16480_chip_info adis16480_chip_info[] = {
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.max_dec_rate = 4250,
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.filter_freqs = adis16495_def_filter_freqs,
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.has_pps_clk_mode = true,
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.adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts),
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/* 20 elements of 16bits */
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.adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
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ADIS16495_BURST_MAX_DATA * 2),
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},
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[ADIS16497_1] = {
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.channels = adis16485_channels,
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@ -1040,7 +1061,9 @@ static const struct adis16480_chip_info adis16480_chip_info[] = {
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.max_dec_rate = 4250,
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.filter_freqs = adis16495_def_filter_freqs,
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.has_pps_clk_mode = true,
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.adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts),
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/* 20 elements of 16bits */
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.adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
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ADIS16495_BURST_MAX_DATA * 2),
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},
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[ADIS16497_2] = {
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.channels = adis16485_channels,
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@ -1054,7 +1077,9 @@ static const struct adis16480_chip_info adis16480_chip_info[] = {
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.max_dec_rate = 4250,
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.filter_freqs = adis16495_def_filter_freqs,
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.has_pps_clk_mode = true,
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.adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts),
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/* 20 elements of 16bits */
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.adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
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ADIS16495_BURST_MAX_DATA * 2),
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},
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[ADIS16497_3] = {
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.channels = adis16485_channels,
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@ -1068,10 +1093,118 @@ static const struct adis16480_chip_info adis16480_chip_info[] = {
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.max_dec_rate = 4250,
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.filter_freqs = adis16495_def_filter_freqs,
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.has_pps_clk_mode = true,
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.adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts),
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/* 20 elements of 16bits */
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.adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
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ADIS16495_BURST_MAX_DATA * 2),
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},
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};
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static bool adis16480_validate_crc(const u16 *buf, const u8 n_elem, const u32 crc)
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{
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u32 crc_calc;
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u16 crc_buf[15];
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int j;
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for (j = 0; j < n_elem; j++)
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crc_buf[j] = swab16(buf[j]);
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crc_calc = crc32(~0, crc_buf, n_elem * 2);
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crc_calc ^= ~0;
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return (crc == crc_calc);
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}
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static irqreturn_t adis16480_trigger_handler(int irq, void *p)
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{
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struct iio_poll_func *pf = p;
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struct iio_dev *indio_dev = pf->indio_dev;
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struct adis16480 *st = iio_priv(indio_dev);
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struct adis *adis = &st->adis;
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int ret, bit, offset, i = 0;
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__be16 *buffer;
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u32 crc;
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bool valid;
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adis_dev_lock(adis);
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if (adis->current_page != 0) {
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adis->tx[0] = ADIS_WRITE_REG(ADIS_REG_PAGE_ID);
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adis->tx[1] = 0;
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ret = spi_write(adis->spi, adis->tx, 2);
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if (ret) {
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dev_err(&adis->spi->dev, "Failed to change device page: %d\n", ret);
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adis_dev_unlock(adis);
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goto irq_done;
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}
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adis->current_page = 0;
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}
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ret = spi_sync(adis->spi, &adis->msg);
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if (ret) {
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dev_err(&adis->spi->dev, "Failed to read data: %d\n", ret);
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adis_dev_unlock(adis);
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goto irq_done;
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}
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adis_dev_unlock(adis);
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/*
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* After making the burst request, the response can have one or two
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* 16-bit responses containing the BURST_ID depending on the sclk. If
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* clk > 3.6MHz, then we will have two BURST_ID in a row. If clk < 3MHZ,
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* we have only one. To manage that variation, we use the transition from the
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* BURST_ID to the SYS_E_FLAG register, which will not be equal to 0xA5A5. If
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* we not find this variation in the first 4 segments, then the data should
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* not be valid.
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*/
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buffer = adis->buffer;
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for (offset = 0; offset < 4; offset++) {
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u16 curr = be16_to_cpu(buffer[offset]);
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u16 next = be16_to_cpu(buffer[offset + 1]);
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if (curr == ADIS16495_BURST_ID && next != ADIS16495_BURST_ID) {
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offset++;
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break;
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}
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}
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if (offset == 4) {
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dev_err(&adis->spi->dev, "Invalid burst data\n");
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goto irq_done;
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}
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crc = be16_to_cpu(buffer[offset + 16]) << 16 | be16_to_cpu(buffer[offset + 15]);
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valid = adis16480_validate_crc((u16 *)&buffer[offset], 15, crc);
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if (!valid) {
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dev_err(&adis->spi->dev, "Invalid crc\n");
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goto irq_done;
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}
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for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->masklength) {
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/*
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* When burst mode is used, temperature is the first data
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* channel in the sequence, but the temperature scan index
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* is 10.
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*/
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switch (bit) {
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case ADIS16480_SCAN_TEMP:
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st->data[i++] = buffer[offset + 1];
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break;
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case ADIS16480_SCAN_GYRO_X ... ADIS16480_SCAN_ACCEL_Z:
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/* The lower register data is sequenced first */
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st->data[i++] = buffer[2 * bit + offset + 3];
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st->data[i++] = buffer[2 * bit + offset + 2];
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break;
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}
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}
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iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp);
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irq_done:
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iio_trigger_notify_done(indio_dev->trig);
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return IRQ_HANDLED;
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}
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static const struct iio_info adis16480_info = {
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.read_raw = &adis16480_read_raw,
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.write_raw = &adis16480_write_raw,
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@ -1341,7 +1474,8 @@ static int adis16480_probe(struct spi_device *spi)
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st->clk_freq = st->chip_info->int_clk;
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}
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ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL);
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ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev,
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adis16480_trigger_handler);
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if (ret)
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return ret;
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