Merge branch 'topic/at_xdmac' into for-linus
This commit is contained in:
commit
939b6ef378
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@ -22,7 +22,7 @@ dma1: dma-controller@f0004000 {
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compatible = "atmel,sama5d4-dma";
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reg = <0xf0004000 0x200>;
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interrupts = <50 4 0>;
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#dma-cells = <2>;
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#dma-cells = <1>;
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};
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@ -109,7 +109,7 @@ config AT_HDMAC
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config AT_XDMAC
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tristate "Atmel XDMA support"
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depends on (ARCH_AT91 || COMPILE_TEST)
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depends on ARCH_AT91
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select DMA_ENGINE
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help
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Support the Atmel XDMA controller.
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@ -562,6 +562,7 @@ at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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struct scatterlist *sg;
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int i;
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u32 cfg;
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unsigned int xfer_size = 0;
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if (!sgl)
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return NULL;
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@ -619,15 +620,15 @@ at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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| (i == sg_len - 1 ? 0 : AT_XDMAC_MBR_UBC_NDE) /* descriptor fetch */
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| len / (1 << at_xdmac_get_dwidth(cfg)); /* microblock length */
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dev_dbg(chan2dev(chan),
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"%s: lld: mbr_sa=0x%08x, mbr_da=0x%08x, mbr_ubc=0x%08x\n",
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__func__, desc->lld.mbr_sa, desc->lld.mbr_da, desc->lld.mbr_ubc);
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"%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
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__func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
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/* Chain lld. */
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if (prev) {
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prev->lld.mbr_nda = desc->tx_dma_desc.phys;
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dev_dbg(chan2dev(chan),
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"%s: chain lld: prev=0x%p, mbr_nda=0x%08x\n",
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__func__, prev, prev->lld.mbr_nda);
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"%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
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__func__, prev, &prev->lld.mbr_nda);
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}
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prev = desc;
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@ -637,12 +638,13 @@ at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
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__func__, desc, first);
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list_add_tail(&desc->desc_node, &first->descs_list);
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xfer_size += len;
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}
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spin_unlock_bh(&atchan->lock);
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first->tx_dma_desc.flags = flags;
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first->xfer_size = sg_len;
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first->xfer_size = xfer_size;
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first->direction = direction;
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return &first->tx_dma_desc;
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@ -660,8 +662,8 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
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int i;
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u32 cfg;
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dev_dbg(chan2dev(chan), "%s: buf_addr=0x%08x, buf_len=%d, period_len=%d, dir=%s, flags=0x%lx\n",
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__func__, buf_addr, buf_len, period_len,
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dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
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__func__, &buf_addr, buf_len, period_len,
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direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags);
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if (!is_slave_direction(direction)) {
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@ -688,8 +690,8 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
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}
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spin_unlock_bh(&atchan->lock);
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dev_dbg(chan2dev(chan),
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"%s: desc=0x%p, tx_dma_desc.phys=0x%08x\n",
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__func__, desc, desc->tx_dma_desc.phys);
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"%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
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__func__, desc, &desc->tx_dma_desc.phys);
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if (direction == DMA_DEV_TO_MEM) {
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desc->lld.mbr_sa = atchan->per_src_addr;
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@ -699,7 +701,7 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
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desc->lld.mbr_sa = buf_addr + i * period_len;
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desc->lld.mbr_da = atchan->per_dst_addr;
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cfg = atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG];
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};
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}
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desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
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| AT_XDMAC_MBR_UBC_NDEN
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| AT_XDMAC_MBR_UBC_NSEN
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@ -707,15 +709,15 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
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| period_len >> at_xdmac_get_dwidth(cfg);
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dev_dbg(chan2dev(chan),
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"%s: lld: mbr_sa=0x%08x, mbr_da=0x%08x, mbr_ubc=0x%08x\n",
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__func__, desc->lld.mbr_sa, desc->lld.mbr_da, desc->lld.mbr_ubc);
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"%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
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__func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
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/* Chain lld. */
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if (prev) {
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prev->lld.mbr_nda = desc->tx_dma_desc.phys;
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dev_dbg(chan2dev(chan),
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"%s: chain lld: prev=0x%p, mbr_nda=0x%08x\n",
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__func__, prev, prev->lld.mbr_nda);
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"%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
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__func__, prev, &prev->lld.mbr_nda);
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}
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prev = desc;
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@ -729,8 +731,8 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
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prev->lld.mbr_nda = first->tx_dma_desc.phys;
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dev_dbg(chan2dev(chan),
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"%s: chain lld: prev=0x%p, mbr_nda=0x%08x\n",
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__func__, prev, prev->lld.mbr_nda);
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"%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
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__func__, prev, &prev->lld.mbr_nda);
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first->tx_dma_desc.flags = flags;
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first->xfer_size = buf_len;
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first->direction = direction;
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@ -762,8 +764,8 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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| AT_XDMAC_CC_MBSIZE_SIXTEEN
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| AT_XDMAC_CC_TYPE_MEM_TRAN;
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dev_dbg(chan2dev(chan), "%s: src=0x%08x, dest=0x%08x, len=%d, flags=0x%lx\n",
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__func__, src, dest, len, flags);
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dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
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__func__, &src, &dest, len, flags);
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if (unlikely(!len))
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return NULL;
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@ -791,7 +793,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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while (remaining_size) {
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struct at_xdmac_desc *desc = NULL;
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dev_dbg(chan2dev(chan), "%s: remaining_size=%u\n", __func__, remaining_size);
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dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size);
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spin_lock_bh(&atchan->lock);
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desc = at_xdmac_get_desc(atchan);
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@ -812,7 +814,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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else
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xfer_size = remaining_size;
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dev_dbg(chan2dev(chan), "%s: xfer_size=%u\n", __func__, xfer_size);
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dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size);
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/* Check remaining length and change data width if needed. */
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if (!((src_addr | dst_addr | xfer_size) & 7)) {
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@ -843,8 +845,8 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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desc->lld.mbr_cfg = chan_cc;
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dev_dbg(chan2dev(chan),
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"%s: lld: mbr_sa=0x%08x, mbr_da=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
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__func__, desc->lld.mbr_sa, desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
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"%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
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__func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
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/* Chain lld. */
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if (prev) {
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@ -879,7 +881,7 @@ at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
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struct list_head *descs_list;
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enum dma_status ret;
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int residue;
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u32 cur_nda;
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u32 cur_nda, mask, value;
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u8 dwidth = at_xdmac_get_dwidth(atchan->cfg[AT_XDMAC_CUR_CFG]);
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ret = dma_cookie_status(chan, cookie, txstate);
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@ -899,14 +901,22 @@ at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
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*/
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if (!desc->active_xfer) {
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dma_set_residue(txstate, desc->xfer_size);
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spin_unlock_bh(&atchan->lock);
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return ret;
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}
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residue = desc->xfer_size;
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/* Flush FIFO. */
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at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
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while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
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cpu_relax();
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/*
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* Flush FIFO: only relevant when the transfer is source peripheral
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* synchronized.
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*/
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mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
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value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
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if ((atchan->cfg[AT_XDMAC_CUR_CFG] & mask) == value) {
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at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
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while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
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cpu_relax();
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}
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cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
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/*
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@ -927,8 +937,8 @@ at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
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dma_set_residue(txstate, residue);
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dev_dbg(chan2dev(chan),
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"%s: desc=0x%p, tx_dma_desc.phys=0x%08x, tx_status=%d, cookie=%d, residue=%d\n",
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__func__, desc, desc->tx_dma_desc.phys, ret, cookie, residue);
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"%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
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__func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue);
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return ret;
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}
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@ -1384,6 +1394,11 @@ static int at_xdmac_probe(struct platform_device *pdev)
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dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
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dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
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dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
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/*
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* Without DMA_PRIVATE the driver is not able to allocate more than
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* one channel, second allocation fails in private_candidate.
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*/
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dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
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atxdmac->dma.dev = &pdev->dev;
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atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
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atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
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@ -1393,7 +1408,6 @@ static int at_xdmac_probe(struct platform_device *pdev)
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atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
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atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
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atxdmac->dma.device_control = at_xdmac_control;
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atxdmac->dma.chancnt = nr_channels;
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atxdmac->dma.device_slave_caps = at_xdmac_device_slave_caps;
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/* Disable all chans and interrupts. */
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