Merge branch 'drm-fixes-3.16' of git://people.freedesktop.org/~agd5f/linux into drm-next
mode validation, deep color and pageflipping fixes. * 'drm-fixes-3.16' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: Fix radeon_irq_kms_pflip_irq_get/put() imbalance Revert "drm/radeon: remove drm_vblank_get|put from pflip handling" drm/radeon: improve dvi_mode_valid drm/radeon: update mode_valid testing for DP drm/radeon: Use dce5/6 hdmi deep color clock setup also on dce8+
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commit
937a0c7987
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@ -1052,7 +1052,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
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int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
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/* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
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if (ASIC_IS_DCE5(rdev) && !ASIC_IS_DCE8(rdev) &&
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if (ASIC_IS_DCE5(rdev) &&
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(encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
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(radeon_crtc->bpc > 8))
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clock = radeon_crtc->adjusted_clock;
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@ -1288,17 +1288,15 @@ static int radeon_dvi_mode_valid(struct drm_connector *connector,
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(radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
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(radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B))
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return MODE_OK;
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else if (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_A) {
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if (ASIC_IS_DCE6(rdev)) {
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/* HDMI 1.3+ supports max clock of 340 Mhz */
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if (mode->clock > 340000)
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return MODE_CLOCK_HIGH;
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else
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return MODE_OK;
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} else
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else if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector->edid)) {
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/* HDMI 1.3+ supports max clock of 340 Mhz */
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if (mode->clock > 340000)
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return MODE_CLOCK_HIGH;
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} else
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else
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return MODE_OK;
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} else {
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return MODE_CLOCK_HIGH;
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}
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}
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/* check against the max pixel clock */
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@ -1549,6 +1547,8 @@ out:
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static int radeon_dp_mode_valid(struct drm_connector *connector,
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struct drm_display_mode *mode)
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{
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struct drm_device *dev = connector->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_connector *radeon_connector = to_radeon_connector(connector);
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struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
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@ -1579,14 +1579,23 @@ static int radeon_dp_mode_valid(struct drm_connector *connector,
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return MODE_PANEL;
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}
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}
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return MODE_OK;
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} else {
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if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
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(radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
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(radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
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return radeon_dp_mode_valid_helper(connector, mode);
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else
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return MODE_OK;
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} else {
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if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector->edid)) {
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/* HDMI 1.3+ supports max clock of 340 Mhz */
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if (mode->clock > 340000)
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return MODE_CLOCK_HIGH;
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} else {
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if (mode->clock > 165000)
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return MODE_CLOCK_HIGH;
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}
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}
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}
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return MODE_OK;
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}
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static const struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = {
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@ -358,8 +358,9 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
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spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
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drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
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radeon_fence_unref(&work->fence);
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radeon_irq_kms_pflip_irq_get(rdev, work->crtc_id);
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radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
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queue_work(radeon_crtc->flip_queue, &work->unpin_work);
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}
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@ -460,6 +461,12 @@ static void radeon_flip_work_func(struct work_struct *__work)
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base &= ~7;
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}
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r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id);
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if (r) {
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DRM_ERROR("failed to get vblank before flip\n");
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goto pflip_cleanup;
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}
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/* We borrow the event spin lock for protecting flip_work */
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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@ -474,6 +481,16 @@ static void radeon_flip_work_func(struct work_struct *__work)
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return;
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pflip_cleanup:
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if (unlikely(radeon_bo_reserve(work->new_rbo, false) != 0)) {
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DRM_ERROR("failed to reserve new rbo in error path\n");
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goto cleanup;
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}
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if (unlikely(radeon_bo_unpin(work->new_rbo) != 0)) {
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DRM_ERROR("failed to unpin new rbo in error path\n");
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}
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radeon_bo_unreserve(work->new_rbo);
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cleanup:
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drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
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radeon_fence_unref(&work->fence);
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