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drm/amd/powerplay: enable clock gating for Fiji. 

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
This commit is contained in:
Eric Huang 2015-11-12 17:30:52 -05:00 committed by Alex Deucher
parent 6cec2655fa
commit 92b05d827d
1 changed files with 8 additions and 1 deletions
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9
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
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@ -917,7 +917,14 @@ static int fiji_start_smu(struct pp_smumgr *smumgr)
}
/* To initialize all clock gating before RLC loaded and running.*/
/*PECI_InitClockGating(peci);*/
cgs_set_clockgating_state(smumgr->device,
AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
cgs_set_clockgating_state(smumgr->device,
AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
cgs_set_clockgating_state(smumgr->device,
AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
cgs_set_clockgating_state(smumgr->device,
AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
/* Setup SoftRegsStart here for register lookup in case
* DummyBackEnd is used and ProcessFirmwareHeader is not executed