drm/radeon/dpm: pull in phase shedding limits from atom
Required for dpm on SI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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32ce4652dc
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929ee7a8b3
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@ -806,7 +806,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev)
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}
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}
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/* clock dependancy tables */
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/* clock dependancy tables, shedding tables */
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if (power_info->pplib.usTableSize >= sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE4)) {
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if (power_info->pplib4.usVddcDependencyOnSCLKOffset) {
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dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
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@ -858,6 +858,32 @@ int r600_parse_extended_power_table(struct radeon_device *rdev)
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le16_to_cpu(clk_v->entries[0].usVddci);
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}
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}
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if (power_info->pplib4.usVddcPhaseShedLimitsTableOffset) {
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ATOM_PPLIB_PhaseSheddingLimits_Table *psl =
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(ATOM_PPLIB_PhaseSheddingLimits_Table *)
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(mode_info->atom_context->bios + data_offset +
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le16_to_cpu(power_info->pplib4.usVddcPhaseShedLimitsTableOffset));
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rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries =
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kzalloc(psl->ucNumEntries *
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sizeof(struct radeon_phase_shedding_limits_entry),
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GFP_KERNEL);
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if (!rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries)
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return -ENOMEM;
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for (i = 0; i < psl->ucNumEntries; i++) {
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rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk =
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le16_to_cpu(psl->entries[i].usSclkLow) |
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(psl->entries[i].ucSclkHigh << 16);
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rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk =
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le16_to_cpu(psl->entries[i].usMclkLow) |
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(psl->entries[i].ucMclkHigh << 16);
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rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage =
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le16_to_cpu(psl->entries[i].usVoltage);
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}
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rdev->pm.dpm.dyn_state.phase_shedding_limits_table.count =
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psl->ucNumEntries;
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}
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}
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/* cac data */
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@ -909,4 +935,6 @@ void r600_free_extended_power_table(struct radeon_device *rdev)
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kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
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if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries)
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kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);
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if (rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries)
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kfree(rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries);
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}
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@ -1270,6 +1270,17 @@ struct radeon_cac_leakage_table {
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struct radeon_cac_leakage_entry *entries;
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};
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struct radeon_phase_shedding_limits_entry {
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u16 voltage;
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u32 sclk;
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u32 mclk;
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};
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struct radeon_phase_shedding_limits_table {
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u32 count;
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struct radeon_phase_shedding_limits_entry *entries;
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};
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struct radeon_dpm_dynamic_state {
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struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
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struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
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@ -1283,6 +1294,7 @@ struct radeon_dpm_dynamic_state {
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u16 vddc_vddci_delta;
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u16 min_vddc_for_pcie_gen2;
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struct radeon_cac_leakage_table cac_leakage_table;
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struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
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};
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struct radeon_dpm_fan {
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